本研究為將時間放大技術應用在二階游標尺延遲線之時間數位轉換器，以解決游標尺延遲線架構在面積、功率消耗、及元件匹配度等方面所遭遇的問題，同時能使時間數位轉換器達到更高的時間解析度。在本論文中我們提出了基於在單位增益緩衝器組態下之差動差值放大器的時間放大器架構，其時間增益可藉由改變差動差值放大器之輸出共模電壓而在2~20倍之間做調變，而最大輸入範圍可達到60ps。我們將此時間放大器的增益設定在16倍，並且應用於一個第一級為5位元，而第二級為4位元的二階游標尺延遲線時間數位轉換器中，兩個輸入訊號之間的時間差經過第一級游標尺延遲線做粗略的時間解析之後，殘餘時間會藉由介面電路傳送給時間放大器，第二級游標尺延遲線會再將放大後的殘餘時間做更精細的時間解析。其中第一級和第二級游標尺延遲線的解析度皆為45ps，此數值則是來自於組成延遲元件的反相器之傳輸延遲。
一個9位元的時間數位轉換器使用TSMC CMOS 0.18um 1P6M製程來實現，根據模擬結果顯示，其時間解析度可達到3ps，而最大可量測時間範圍為1.44ns，DNL及INL則分別介於-0.5LSB~+0.9LSB和-0.8LSB~+1LSB之間。

This paper describes the design of using time amplification in time-to-digital converter (TDC) with two level vernier delay line (VDL), which is used to solve the limitations of chip area, power consumption, and device mismatching of VDL in 10 picoseconds or less time resolution. In this paper, we proposed a new TA architecture based on differential difference amplifier (DDA) in unity gain buffer configuration. The gain is adjustable between 2 to 20, which can be controlled by the output common-mode voltage of DDA, and the input range can up to about 60ps. The proposed TA is applied to a 9-bit two-stage TDC. The TDC is using a two-stage VDL structure. The first stage has five bits, and the second stage has four bits. The TA with a gain of 16 is placed in between the two VDLs. After the five most significant bits (MSB) time-to-digital conversion is first carried out by the coarse VDL, the time residual of the coarse VDL is transferred to the TA through an interface circuit. The fine VDL then converts the amplified time residual to the four least significant bits (LSB). Both VDLs have designed with the same timing resolution of about 40ps, which is the intrinsic delay of inverters.
A 9-bit two-stage vernier delay line time-to-digital converter has been proposed using TSMC 0.18um CMOS process. Simulation result shows that the overall time resolution of the TDC is 3ps, and the full input range is about 1.44ns. Besides, the DNL and INL are -0.5~0.9 LSB and -0.8~1 LSB, respectively.

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