近年來，物聯網的應用發展快速，使得高速，低耗能和低成本的非揮發性記憶體需求日益增加。而在市場上，快閃記憶體更在近年來已經成為非揮發性記憶體的主流。然而，快閃記憶體需要高電壓來進行寫入和消除資料，而且其操作速度偏慢，對於未來的高速5G、物聯網的產品已不符需求。
在下世代的非揮發性記憶體當中(例如:ReRAM、STT-MRAM…等)非常適合用於穿戴式裝置中，其中以自旋力矩轉移-磁阻式隨機存取記憶體(STT-MRAM)，因為其存取速度較快、耐久性高、非揮發性三大優勢，被認為是目前極具發展潛力之新興記憶體。為了解決記憶體系統之效能瓶頸，利用新興非揮發性記憶體作為儲存級記憶體(SLM)，在儲存裝置及主記憶體間扮演溝通之橋梁。因此，自旋力矩轉移-磁阻式隨機存取記憶體在此新領域中擁有極大的潛力。
在本碩士論文中將探討自旋力矩轉移-磁阻式隨機存取記憶體在存取上會面臨的挑戰，並提出一電壓感測放大器電路解決以下問題，以提升讀取效能:
1. 自旋力矩轉移-磁阻式隨機存取記憶體元件的阻值偏低，在電壓感測下，位元線放電到地速度過快，感測裕度無法拉開至足夠電壓差距，造成讀取良率低落。
2. 越高的讀取電壓越容易造成讀取干擾(Read disturb)現象，而傳統感測方法在低讀取電壓下讀取良率低落。
3. 自旋力矩轉移-磁阻式隨機存取記憶體之穿隧式磁阻比例(TMR-Ratio)小及製程飄移現象，造成資料0與資料1之阻值差異性小，也會造成讀取良率低落。
因此，在此篇論文中提出具有製程變異容忍及預先放大感測裕度之電壓增強回授架構之裕度增強電壓感測放大器 (VEF-VSA)。我們提出的VEF-VS相比於傳統電壓感測放大器可容忍之TMR-比例提升至30%，且可容忍3倍以下之讀取電壓和在相同讀取良率可以減少2.2-2.8倍的讀取速度，並相對傳統電流及傳統電壓讀取在相同讀取良率可減少74.1%及61.5%的能量消耗，並可放大12.1倍感測裕度和減少位元線對讀取速度的影響。
我們以容量為512kb的電阻式記憶體來實作我們提出的架構。使用台積電55奈米製程。在正常操作電壓為1V下，量測提出之電路讀取速度為1 ns而提出之電路最低讀取電壓為100mV。

In recent years, the application of IoT has developed rapidly and making the demand for high speed, low power and low cost non-volatility memory increasing. In the market, flash memory has become the mainstream of non-volatile memory in recent years. However, flash memory requires high voltage for programing and erasing data, and its operation speed is slow, which is not meet the requirements for future smarter edge device and IoT products.
Among the emerging non-volatile memory (e.g. ReRAM, STT-MRAM…etc.) is very suitable for use in wearable devices, where Spin Torque Transfer-Magneto resistive Random Access Memory (STT-MRAM), Because of its fast access speed, high endurance and non-volatile advantages, it is considered to be an emerging memory with great development potential. In order to solve the performance bottleneck of the memory system, the emerging non-volatile memory (eNVM) is used as the storage-level memory (SLM), which acts as a bridge between the storage device and the main memory. Therefore, STT-MRAM has great potential in this new field.
In this paper, we will discuss the issue of STT-MRAM in sensing, and proposed a voltage mode sense amplifier to solve the following problems to improve the read performance:
1. The low resistance value of STT-MRAM cell will cause the bit-line discharge to ground too rapid to generate enough voltage difference between BL and BLB in voltage sensing, resulting in low sensing yield.
2. High read voltage will increase read disturb rate. However, the conventional scheme suffers low sensing yield at low read voltage operation.
3. The low Tunneling Magnetoresistance Ratio (TMR-ratio) of STT-MRAM cell and process variation effect, resulting in small resistance difference between data-0 and data-1. Therefore, leading to low sensing yield.
Therefore, in this paper, a margin-enhanced voltage sense amplifier (VEF-VSA) with a voltage-enhanced feedback architecture with process variation tolerance and pre-amplified sensing margin is proposed. Our proposed VEF-VSA can tolerate TMR-ratio up to 30% compared to conventional voltage sense amplifiers(CNV-LVSA). At the same sensing yield, this work can reduce reading voltages of more than 3 times and improve reading speed by 2.2-2.8 times. Compared with the conventional current and the conventional voltage reading (CNV-CSA and CNV-VSA), proposed VEF-VSA can reduce the energy consumption by 74.1% and 61.5%, enlarge the sensing margin by 12.1 times and reduce the influence of bit-line length on the reading speed.
We implemented our proposed sensing scheme with a 512 kb CRRAM memory. Use TSMC's 55nm process. At a normal operating voltage of 1V, the measured access time is 1 ns and the minimum read voltage is 100mV.

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