簡易檢索 / 詳目顯示

研究生: 張耀文
論文名稱: 免於電荷注入誤差之電荷式電容量測方法研究與應用
A Study of Charge-Injection-Error-Free Charge-Based Capacitance Measurement and Its Applications
指導教授: 金雅琴
口試委員:
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2010
畢業學年度: 99
語文別: 英文
論文頁數: 106
中文關鍵詞: 電容量測電荷式電容量測方法電荷注入接線電容金氧半電晶體電容
外文關鍵詞: Charge-based capacitance measurement, CBCM, interconnect capacitance, MOS capacitance, charge injection, STI stress, CMP, dummy fill
相關次數: 點閱:3下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 電荷式的電容量測方法擁有很高的量測精準度以及易於操作之特性,這幾年來受到很大的矚目,並且被廣泛的應用在後段製程金屬接線電容的量測上。在本論文中,一種新穎而改良的電荷式電容量測方法被提出來。而由於此一新的電荷式電容量測方法可以完全避免掉在傳統的電荷式電容量測方法中所免除不了的,由電荷注入現象所造成的誤差,所以我們稱此新的電容量測方法為免於電荷注入誤差之電荷式電容量測方法。
    在特別設計的佈局安排下,免於電荷注入誤差之電荷式電容量測方法可以有效率的用來做大量的電容量測。對先進的電路設計而言,正確的金屬接線電容的模型非常重要,而接線電容模型的萃取就正好需要大量的電容量測結果。此外,藉由此電荷式電容量測方法,這也是第一次能真正直接監測到在CMP製程中浮動電位的dummy-fill對金屬接線電容的影響。再者,我們更成功的將電荷式電容量測方法的應用,從定電容量測拓展到有電壓變化的電容。本論文將呈現數個小尺寸的金氧半電晶體閘極電容量測的例子及其特殊應用。


    Abstract Acknowledgements List of Contents List of Figures List of Tables 1. Introduction 1.1 Motivation 1.2 Contributions 1.3 Dissertation Organization 2. Review of Charge-Based Capacitance Measurement (CBCM) 2.1 Test Structures and Operations of CBCM 2.2 Limitations of CBCM Approaches 2.3 Summary 3. Charge-Injection-Error-Free Charge-Based Capacitance Measurement (CIEF CBCM) 3.1 Introduction 3.2 Charge Injection in CBCM Operations and the Induced Errors 3.3 Charge-Injection-Error-Free (CIEF) CBCM 3.4 Demonstration of CIEF CBCM 3.5 Summary 4. CIEF CBCM for Interconnect Capacitance Characterization 4.1 Introduction 4.2 CIEF CBCM Test Pattern Design for Massive Data Collection 4.3 CIEF CBCM for Interconnect Capacitance Characterizations 4.3.1 Characterizations of Interconnect Capacitances 4.3.2 Validation by TCAD Simulation 4.3.3 Validation by RC Circuit 4.4 Investigation into Floating Dummy Fill Effect 4.4.1 CMP Process and Dummy-Fills Insertion 4.4.2 Characterization of Interconnect Capacitance with Floating Dummy-Fills Inserted 4.4.3 Dummy Pattern Design for Circuit Performance Optimization 4.5 Summary 5. CIEF CBCM for Real MOSFET Capacitance Characterization 5.1 Introduction 5.2 CIEF CBCM for Bias-Dependent Capacitance Extraction 5.2.1 Experimental Setup for Cgg Extraction 5.2.2 Experimental Results 5.3 Decoupled C-V Method for Effective Channel Length Extraction 5.3.1 Decoupled C-V Method 5.3.2 Measurement of Overlap Capacitance 5.4 Intrinsic Cgc Measurement for the Study of STI Stress Effect 5.4.1 STI Stress Effect on MOSFET Devices 5.4.2 Mobility Extraction and Split C-V Method 5.4.3 Measurement of Intrinsic Cgc of MOSFET Devices 5.4.4 Mobility Extraction and Mobility Degradation Due to STI Stress Effect 5.5 Characterization of MOSFET Intrinsic Capacitance 5.6 Summary 6. Conclusion Appendix A. Extraction of MOSFET Intrinsic Capacitances, Cgd and Cgs References

    [1] Keith Buchanan, “The evolution of interconnect technology for silicon integrated circuitry”, 2002 GaAsMANTECH Conference.
    [2] J. J. Estabil, H. S. Rathore, and F. Dorleans, “The effect of metal thickness on electromigration-induced extrusion shorts in submicron technology,” Reliability Physics Symposium, pp. 57-63, 1991.
    [3] C. Christiansen, J. Gambino, J. Therrien, D. Hunt, and J. Gill, “Effect of Wire Thickness on Electromigration and Stress Migration Lifetime of Cu”, Physical and Failure Analysis of Integrated Circuits, pp. 349-354, July 2006.
    [4] D. Sylvester and C. Hu, “Analytical Modeling and Characterization of Deep-Submicrometer Interconnect,” Proceedings of the IEEE, Vol. 89, No. 5, pp. 634-664, May 2001.
    [5] X. W. Lin and D. Pramanik, “Future interconnect technologies and copper metallization,” Solid State Technology, pp. 63-79, Oct 1998.
    [6] R. K. Krishnamurthy, A. Alvandpour, S. Mathew, M. Anders, V. De, and S. Borkar; “High–performance, low–power, and leakage–tolerance challenges for sub–70nm microprocessor circuits,” European Solid-State Circuits Conference, p.315-321, 2002.
    [7] D. Sylvester, C. Hu, O. S. Nakagawa, and S-Y. Oh, “Interconnect Scaling: Signal Integrity and Performance in Future High-Speed CMOS Designs,” Symp. on VLSI Technology, pp. 42-43, 1998.
    [8] F. Mendoza-Hernandez, M. Linares, and V. H. Champac, “The noise immunity of dynamic digital circuits with technology scaling,” Int. Symp. on Circuits and Systems, pp. 23-26, 2004.
    [9] D. S. Boning and J. E. Chung, “Statistical Metrology – Measurement and Modeling of Variation for Advanced Process Development and Design Rule Generation,” Int. Conference on Characterization and Metrology for ULSI Technology, 1998.
    [10] J. K. Wee, Y. J. Park, H. S. Min, D. H. Cho, M. H. Seung, and H. S. Park, “Measurement and characterization of multilayered interconnect capacitance for deep-submicron VLSI technology,” IEEE Trans. Semiconductor Manufacturing, pp. 636-644, Nov. 1998.
    [11] A. Husain, “Models for Interconnect Capacitance Extraction,” Int. Symp. on Quality Electronic Design, pp. 167-172, 2001
    [12] D. O. Ouma, D. S. Boning, J. E. Chung, W. G. Easter, V. Saxena, S. Misra, and A. Crevasse, “Characterization and Modeling of Oxide Chemical-Mechanical Polishing Using Planarization Length and Pattern Density Concepts,” IEEE Trans. Semiconductor Manufacturing, Vol.15 , pp. 232-244, May 2002
    [13] A. B. Kahng, G. Robins, A. Singh, and A. Zelikovsky, “Filling Algorithms and Analyses for Layout Density Control,” IEEE Trans. CAD of IC and Systems, pp. 445-462, April 1999.
    [14] B. E. Stine, D. S. Boning, J. E. Chung, L. Camilletti, F. Kruppa, E. R. Equi, W. Loh, S. Prasad, M. Muthukrishnan, D. Towery, M. Berman, and A. Kapoor, “The Physical and Electrical Effects of Metal-fill Patterning Practices for Oxide Chemical-Mechanical Polishing Processes,” IEEE Trans. Electron Devices, pp. 665-679, March 1998.
    [15] Y. Chen, A. B. Kahng, G. Robins, and A. Zelikovsky, “Area Fill Synthesis for Uniform Layout Density,” IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, pp. 1132-1147, 2002.
    [16] J. C. Chen, B. W. McGaughy, D. Sylvester, and C. Hu, “An On-Chip, Attofarad Interconnect Charge-Based Capacitance Measurement (CBCM) Technique,” IEDM 1996, pp. 3.4.1-3.4.4.
    [17] B. Froment, F. Paillardet, M. Bely, J. Cluzel, E. Granger, M. Haond, and L. Dugoujon, “Ultra Low Capacitance Measurements in Multilevel Metallisation CMOS by Using a Built-in Electron-Meter,” IEDM 1999, pp. 37.2.1-37.2.4.
    [18] T. Kunikiyo, T. Watanabe, T. Kanamoto, H. Asazato, M. Shirota, K. Eikyu, Y. Ajioka, H. Makino, K. Ishikawa, S. Iwade, and Y. Inoue, “Test Structure Measuring Inter- and Intralayer Coupling Capacitance of Interconnection with Subfemtofarad Resolution,” IEEE Trans. Electron Devices, pp. 726-735, May 2004
    [19] A. Brambilla, P. Maffezzoni, L. Bortesi, L. Vendrame, “Measurements and Extractions of Parasitic Capacitances in ULSI Layouts,” IEEE Trans. Electron Devices, pp.2236 – 2247, Nov. 2003
    [20] S. Bothra, G. A. Rezvani, H. Sur, M. Farr, J. N. Shenoy, “Application of Charge Based Capacitance Measurement (CBCM) Technique in Interconnect Process Development,” IEEE Int. Interconnect Technology Conference, pp. 181-183, 1998.
    [21] N. D. Arora and L. Song, “Atto-Farad Measurement and Modeling of On-Chip Coupling Capacitance,” IEEE Electron Device Letters, pp. 92-94, Feb, 2004.
    [22] L. Vendrame, L. Bortesi, F. Cattane, and A. Bogliolo, “Crosstalk-Based Capacitance Measurements: Theory and Applications,” IEEE Trans. On Semiconductor Manufacturing, pp. 67-77, Feb, 2006.
    [23] Y. W. Chang, H. W. Chang, C. H. Hsieh, H. C. Lai, T. C. Lu, W. Ting, J. Ku, C. Y. Lu, “A Novel Simple CBCM Method Free from Charge Injection-Induced Errors,” Electron Device Letters, pp. 262-264, May 2004.
    [24] Y. W. Chang, H. W. Chang, T. C. Lu, Y. King, W. Ting, J. Ku, C. Y. Lu, “A Novel CBCM Method Free from Charge Injection Induced Errors: Investigation into the Impact of Floating Dummy-Fills on Interconnect Capacitance,” ICMTS 2005, pp. 235-238.
    [25] Y. W. Chang, H. W. Chang, T. C. Lu, Y-C. King, W. Ting, J. Ku, C. Y. Lu, “Charge-Based Capacitance Measurement for Bias-Dependent Capacitance,” Electron Device Letters, pp. 390-392, May, 2006.
    [26] Y. W. Chang, H. W. Chang, T. C. Lu, Y-C. King, K. C. Chen, and C. Y. Lu, “Combining a Novel Charge-Based Capacitance Measurement (CBCM) Technique and Split C-V Method to Specifically Characterize the STI Stress Effect along the Width Direction of MOSFET Devices,” Electron Device Letters, pp. 641-644, June, 2008.
    [27] H. Zhao, R. Kim, A. Paul, M. Luisier, G. Klimeck, F-J. Ma, S. C. Rustagi, G. S. Samudra, N. Singh, G.-Q. Lo, and D-L. Kwong, “Characterization and Modeling of Subfemtofarad Nanowire Capacitance Using the CBCM Technique,” IEEE Electron Device Letters, pp. 526-528, May, 2009.
    [28] B. J. Sheu and C. Hu, “Switch-Induced Error Voltage on a Switched Capacitor,” IEEE J. Solid-State Circuits, Vol. SC-19, No.4, pp. 519-525, Aug 1984.
    [29] Raphael Reference Manual, Avant! Corporation.
    [30] W. Lee, K. Lee, J. Park, T. Kim, Y. Park, and J. Kong, “Investigation of the Capacitance Deviation due to Metal-Fills and the Effective Interconnect Geometry Modeling,” Symp. on Quality Electronic Design, pp. 373-376, March 2003
    [31] J-K. Park, K-H. Lee, J-H. Lee, Y-K. Park, and J-T. Kong, “An Exhaustive Method for Characterizing the Interconnect Capacitance Considering the Floating Dummy-Fills by Employing an Efficient Field Solving Algorithm,” Int. Conference on Simulation of Semiconductor Processes and Devices, pp. 98-101, 2000.
    [32] K-H. Lee, J-K. Park, Y-N. Yoon, D-H. Jung, J-P. Shin, Y-K. Park, and J-T. Kong, “Analyzing the Effects of Floating Dummy-Fills: From Feature Scale Analysis to Full-Chip RC Extraction,” IEEE IEDM, pp.685-688, 2001.
    [33] B. Blampey, B. Flechet, A. Farcy, C. Bermond, O. Cueto, J. Torres, G. Angenieux, “Capacitive impacts of dummies on interconnect propagation performances for integrated circuits of the 65 nm node and below,” IEEE Interconnect Technology Conference, pp. 117-119, 2005.
    [34] H. V. Meer, K. Henson, J. H. Lyu, S. Kubicek, N. Collaert, and K. D. Meyer, “Limitations of Shift-and Ratio Based Leff Extraction Techniques for MOS Transistors with Halo or Pocket Implants,” IEEE. Electron Device Letter, Vol. 21, p.133, Mar. 2000.
    [35]. T. S. Hsieh, Y. W. Chang, W. J. Tsai, and T. C. Lu, “A New Leff Extraction Approach for Devices with Pocket Implants,” IEEE Int. Conference on Microelectronic Test Structure, pp.15-18, 2001.
    [36] J. Koomen, “Investigation of the MOST Channel Conductance in Weak Inversion,” Solid State Electron., Vol. 16, pp. 801-810, 1973.
    [37] K. Romanjek, F. Andrieu, T. Ernst, and G. Ghibaudo, “Improved Split C-V Method for Effective Mobility Extraction in sub-0.1-□m Si MOSFETs,” IEEE Electron Device Letters, Vol. 25, No. 8, pp. 583-585, Aug. 2004.
    [38] E. San Andres, L. Pantisano, J.Ramos, S. Severi, L. Trojman, S. DeGendt, and G. Groeseneken, “RF Split Capacitance-Voltage Measurements of Short-Channel and Leaky MOSFET Devices,” IEEE Electron Device Letters, Vol. 27, No. 9, pp. 772-774, Sept. 2006.
    [39]. C. Gallon, G. Reimbold, G. Ghibaudo, R.A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud, and H. Dansas, “Electrical Analysis of Mechanical Stress Induced by STI in Short MOSFETs Using Externally Applied Stress,” IEEE Trans. Electron Devices, Vol. 51, No. 8, pp. 1254-1261, Aug., 2004.
    [40]. C. S. Smith, “Piezoresistance Effect in Gemanium and Silicon,” Physical Review, Vol. 94, No.1, pp. 42-49, 1954.
    [41] J.C. Guo, C.C.H. Hsu, P. S. Lin, S.S. Chung, “An Accurate “Decoupled C-V” Method for Characterizing Channel and Overlap Capacitances of Miniaturized MOSFET,” VLSI Technology, Systems, and Applications, 1993, pp. 256-260
    [42] Yuan Taur, D. S. Zicherman, D. R. Lombardi, P. J. Restle, C. H. Hsu, H. I. Hanafi, M.R. Wordeman, B. Davari, G. G. Shahidi, “A New Shift and Ratio Method for MOSFET Channel-Length Extraction”, IEEE Electron Device Letters, vol. 13, pp267-269, May 1992. [43] Yuan Taur, “MOSFET Channel Length: Extraction and Interpretation”, IEEE Trans. Electron Devices, vol. ED-47, no. 1, pp. 160-170, Jan. 2000.
    [44] Colin C. McAndrew, Paul A. Layman, “MOSFET Effective Channel Length, Threshold Voltage, and Series Resistance Determination by Robust Optimization”, IEEE Trans. Electron Devices, vol. 39, pp.2298-2311, Oct. 1992
    [45] P. Klein and S. Chladek, “A New Mobility Model for Pocket Implanted Quarter Micron n-MOSFETs and Below,” IEEE Int. Conference on Electronics, Circuits and Systems, pp. 1587-1590, 2001.
    [46] T. Okagaki, M. Tanizawa, T. Uchida, T. Kunikiyo, K. Sonoda, M. Igarashi, K. Ishikawa, T. Takeda, P. Lee, and G. Yokomizo, “Direct Measurement of Stress Dependent Inversion Layer Mobility Using a Novel Test Structure,” Symp. VLSI Tech. Dig., pp. 120-121, 2004.
    [47] G.. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress,” Tech. Dig. IEDM, pp. 827-830, 1999.
    [48] M. Miyamoto, H. Ohta, Y. Kumagai, Y. Sonobe, K. Ishibashi, and Y. Tainaka, “Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics,” IEEE Trans. Electron Devices, Vol. 51, No. 3, pp. 440-443, March, 2004.
    [49] P. Fanini, G. Giuga, S. Schippers, A. Marmiroli, and G. Ferrari, “Modeling of STI-Induced Stress Phenomena in CMOS 90nm Flash Technology,” Solid-State Device Research Conf., pp.401-404, 2004.
    [50] J. C. Guo, S. S. -S. Chung, and C. C.-H. Hsu, “A New Approach to Determine the Effective Channel Length and the Drain-and Source Series Resistance of Miniaturized MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, p. 1811, 1994
    [51] B. Ricco, R.Versari, and D.Esseni , “A Novel Method to Characterize Parasitic Capacitances in MOSFET’s,” IEEE Electron Devices Letters, vol. 16, p. 485, 1994
    C.-L. Huang, J. V. Faricelli, D. A. Antoniadis, N. A. Khalil, and R. A. Rios, “An Accurate Gate Length Extraction Method for Sub-Quarter Micro MOSFET’s,” IEEE Trans. Electron Devices, vol. 43, p.958, 1996
    [52] M.-S. Jo, J.-H.. Kim, S.-K. Kim, H.-S. Toon, and D.-H. Lee, “A Capacitance Method to Determine the Metallurgical Gate-to-Source/Drain Overlap Length of Submicron LDD MOSFET’s,” IEEE Int. Conference on Microelectronic Test Structures, vol. 8, p.151, 1995
    [53] M. M. Lau C. Y. T. Chiang Y. T. Yeow, and Z. Q. Yao, “Measurement of VT and Leff Using MOSFET Gate-Substrate Capacitance,” IEEE Int. Conference on Microelectronic Test Structures, vol. 12, p.152, 1999
    [54] Y. Luo and D. K. Nayak, “Enhancement of CMOS Performance by Process-Induced Stress,” IEEE Trans. Semiconductor Manufacturing, Vol. 18, No. 1, pp. 63-68, Feb. 2005.
    [55] A. Steegen, M. Stucchi, A. Lauwers, and K. Maex, “Silicide Induced Pattern Density and Orientation Dependent Transconductance in MOS Transistors,” Tech. Dig. IEDM, pp. 497-500, 1999.
    [56] A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, F. Otsuka, “Local Mechanical-Stress Control (LMC): A New Technique for CMOS Performance Enhancement,” Tech. Dig. IEDM, pp. 433-436, 2001.
    [57] C.-H. Ge, C.-C. Lin, C.-H. Ko, C.-C. Huang, Y.-C. Huang, B.-W. Chan, B.-C. Perng, C.-C. Sheu, P.-Y. Tsai, L.-G. Yao, C.-L. Wu, T.-L. Lee, C.-J. Chen, C.-T. Wang, S.-C. Lin, Y.-C. Yeo, and C. Hu, “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering,” Tech. Dig. IEDM, pp. 73-76, 2003.
    [58] T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. Mcintyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S, Thompson, and M. Bohr, “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” Tech. Dig. IEDM, pp. 978-980, 2003.
    [59] C. G.. Sodini, T. W. Ekstedt, and J. L. Moll, “Charge accumulation and mobility in thin dielectric MOS transistors, “Solid State Electron., vol. 25, p. 833, 1982
    [60] J. R. Hauser, “Extraction of Experimental Mobility data for MOS Devices,” IEEE Trans. Electron Devices, vol. 43, p.1981, Nov. 1996
    [61] S. S. Chung, “A Charge-Based Capacitance Model of Short Channel MOSFETs,” IEEE Trans. Computer-Aided Design, vol. 8, p.1, Jan. 1989.
    [62] D-H. Cho, S-M. Kang, K-H. Kim, and S-H. Lee, “An Accurate Intrinsic Capacitance Modeling for Deep Submicrometer MOSFET’s,” IEEE Trans. Electron Devices, vol. 42, p. 540, March 1995

    無法下載圖示 全文公開日期 本全文未授權公開 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)

    QR CODE