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研究生: 簡敬庭
Ching, Chien-Ting.
論文名稱: 細長形浮動閘極記憶胞之自我抑制編程特性應用於多層式儲存操作
Multi-level Operation by Self-clamped Program Scheme on Narrow-Bridging Floating Gate NVM
指導教授: 林崇榮
Lin, Chrong-Jung
口試委員: 金雅琴
King, Ya-Chin
池育德
Chih, Yu-Der
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 中文
論文頁數: 66
中文關鍵詞: 多層式儲存單元非揮發性記憶體
外文關鍵詞: MLC, NVM
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  • 在這個普遍利用大數據的時代,高密度的儲存記憶體的需求也持續 性的增加,如何在相同面積上能夠儲存更多的資料,也成為重要的研究 方向,在製程上,不斷縮小限寬;在元件設計上,除了將 2D 結構變成 3D 結構外,還有另一個有效提升儲存密度的方式,那就是多層式儲存 的技術,藉由控制存入浮動閘極的電子數量,可以一次將兩個以上的位 元存入同一個記憶體單元,但也因為需要精細的編成控制,導致多層式 儲存在編程速度上比單層式儲存慢,此外,因為儲存態間的電壓差距變 窄,也使得多層式儲存在元件耐久度上的表現變差。
    本論文提出一細長型浮動閘極可多次操作非揮發記憶體,其特性為 當元件在進行編程時,電子會在細長端的地方發生局部充放電的暫態反 應,使得浮動閘極內的電子數量可以藉由改變電壓與編程時間來做良好 的控制,因此元件的臨界電壓可以被穩定操作於特定的值,此特性可以 應用於多層式儲存應用,藉由穩定的臨界電壓特性,可以使用一次性脈 衝即可完成編成步驟,減少驗證步驟,因此大大縮短的原本編程所需的 時間。
    此細長形浮動閘極可多次操作記憶體編成效率極高,單元間也擁有 良好的抗干擾特性,且在經過寫入抹除的循環測試後,仍然維持優異的 資料穩定性,此外,其局部充放電的暫態特性使得此元件再多層式儲存 應用上有極高的競爭力。


    In this era of widely-used big-data, the demand of high-density data storage has increased continuously. Therefore, how to further increase the data density in a storage device is always attract interests from researchers and developer of new memory technologies. Aggressive scaling of minimum feature size is the most straight forward method to increase cell density. Stacking the cell into a 3D structure has push the storage capability of 3D NAND SSD into Terabit range. Multi-level cells(MLC) is another effective way to increase data densities in mature Flash memory technologies. By controlling the numbers of electrons to place onto the floating gate(FG), may cells can storage more than two bits per cell. To prevent overlapping of the states, program-verify loops are generally build-in to ensure tight threshold voltage distributions on cells across a sizable memory array. These complex program cycles not only increase program times, power consumptions, but might also leads to long-term reliability challenges.
    In this study, a unique self-clamping scheme on the fine-line floating gate MTP cells is presented which with an elongated FG to exhibit significant transient response of localized charging effect, making the amount of electrons in FG can be well-controlled by changing voltage and program time. Since this unique feature can be applied to achieve multiple level storage by one-pulse programming without program-verify loops, the overall programming time can be much reduced.
    This fine-line floating gate MTP cells has high programming efficiency, and great program disturb immunity. And it also has excellent stability andreliability after program-erase cycling test. Besides, the feature of localized charging effect makes this devise competitive for application in MLC.

    摘要 i Abstract ii 致謝 iv 內文目錄 v 附圖目錄 vii 第一章 序論 1 1.1 高密度儲存記憶體發展趨勢 1 1.2 研究動機 2 1.3 論文大綱 3 第二章 多層式儲存記憶體回顧 4 2.1 多層式儲存記憶體回顧 4 2.1.1 Single-Level Cells 5 2.1.2 Multi-Level Cells 5 2.1.3 SLC與MLC的優缺點比較 5 2.2 多層式儲存記憶體編成操作原理 6 2.2.1. ISPP 6 2.2.2. 多次編程步驟 7 2.3 小結 8 第三章 浮動閘極之電阻電容延遲效應 19 3.1 單一複晶矽浮動閘極記憶體元件特性簡介 19 3.1.1 細長型浮動閘極記憶體元件結構 19 3.1.2 細長型浮動閘極記憶體等效電路分析 20 3.1.3 電阻值與臨界電壓變化關係 22 3.1.4 電容值與臨界電壓變化關係 23 3.2 元件之量測結果與模擬結果比較 24 3.3 小結 25 第四章 記憶體元件量測結果與特性分析 35 4.1 記憶體元件操作特性分析 35 4.1.1 抹除特性分析 35 4.1.2 多層式編程特性分析 36 4.1.3 多層式讀取特性分析 37 4.2 記憶體元件可靠度分析 38 4.2.1 編成干擾 38 4.2.2 讀取干擾 39 4.2.3 多層式儲存元件耐久度 40 4.2.4 多層式儲存資料保存特性 40 4.3 小結 41 第五章 應用於多層式儲存之優勢 53 5.1 細長型浮動閘極記憶體之編程速度優勢 53 5.2 小結 54 第六章 總結 59 6.1 細長型浮動閘極記憶體優點分析 59 6.2 結語與未來展望 60 參考文獻 61

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