使用區域性順向基底偏壓的高效能靜態記憶體

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研究生：	許嘉雯
論文名稱：	使用區域性順向基底偏壓的高效能靜態記憶體 High performance SRAM by block forward body bias (FBB)
指導教授：	張彌彰
口試委員:	郭治群馬席彬
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2014
畢業學年度：	102
語文別：	英文
論文頁數：	69
中文關鍵詞：	靜態隨機存取記憶體、導線延遲、順向基底偏壓
外文關鍵詞：	SRAM, interconnect delay, FBB
相關次數：	點閱：2 下載：0
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靜態隨機存取記憶(SRAM)在大多數現今的數位積體電路中提供快速的資料儲存與讀取的功能，因而對這晶片的效能來說，其存取的時間非常重要。然而，隨著製程技術的演進，金屬接線的寄生電阻電容增加，遠端單元的字元線(WL)信號因為阻容延遲而造成嚴重失真並影響到記憶體單元的讀取時間。而這導線的延遲在未來會亦趨嚴重。因此，在技術開發的同時，如何解決這個問題是很重要的。
在這篇論文中，提出了使用區域性順向基底偏壓的方法來克服導線延遲問題。這個方法跟一般的傾向於提高記憶體單元的讀取和寫入能力的偏壓輔助方法不同。我們使用順向基底偏壓來提升導通閘(PG)和下拉閘(PD)電晶體的效能，以減少讀取時間。然而，順向基底偏壓的副作用是待機漏電流的增加。因此，把記憶體陣列分區域，並在每個區域只提供於必要的順向基底偏壓，便可以權衡待機電流的增加與性能增益。
這個方法在這篇論文中採用28奈米256千位元的記憶體陣列來呈現，並證明了可以增加11%的性能增益，同時相對於整個陣列都使用順向基底偏壓時所增加的待機電流，可減少了70％以上。

Static Random Access Memories (SRAM) provide an fast data storage and access for most of today's digital IC's, and thus their access time is important for these IC’s performance. However, due to technology improvement the word-line (WL) pulse of the far-end cells is observed to be severely distorted due to large interconnect RC delay. And the interconnect is predicted to get worse in the future. Thus, it is important to solve this problem for technology development.
In this thesis, a block forward body bias method to overcome the interconnect delay issue is developed. This method is different from the general bias-based assist methods, which tend to improve the read and write margins. We use the forward body bias to improve the pass gate (PG) and pull down (PD) transistors of the far-end cells to reduce the read access time. A side effect of the forward body bias is the increase of standby current. Partition the SRAM columns into blocks and apply only necessary body bias to each block can trade-off the performance gain with standby current increase.
It is demonstrated using 28nm 256k SRAM that the SRAM performance can be improved by 11%, while the standby current increase is reduced by more than 70% compared to full SRAM forward body bias.

Content
Abstract Ⅰ 
摘要 Ⅱ 
Content Ⅳ 
List of Figures Ⅵ 
Chapter 1 Introduction 1 
1 Background 1 
2 Motivation 3 
3 Thesis organization 4 
Chapter 2 Overview of 6T SRAM cell 5 
1 6T SRAM 5 
2 SRAM cell operation 7 
2.1 Write operation 7 
2.2 Read operation 8 
3 SRAM stability issues 9 
3.1 Hold mode statistical noise margin 10 
3.2 Read mode statistical noise margin 11 
3.3 Write margin 13 
3.4 Data retention voltage 14 
4 SRAM Vcc_min 15 
4.1 SRAM failure introduction 15 
4.1 SRAM Vcc_min prediction 16 
Chapter 3 Related SRAM bias assists research 19 
1 Bias assist on read assist 20 
1.1 Reduce WL gate voltage 20 
1.2 Apply reverse bias to reduce NMOS VT 21 
1.3 Reduced bit line charge by lowering the voltage 21 
1.4 Improve latch resilience with increased array VDD 22 
1.5 Current boost by decreasing array VSS 23 
2 Bias assist on write assist 23 
2.1 Boosted word line gate voltage 23 
2.2 Negative BL voltage 24 
2.3 Lower cell array VDD 25 
2.4 Raising array GND 26 
2.5 Increase PU PMOS VT by NW bias 27 
Chapter 4 Proposed block multi-FBB SRAM structure 28 
1 Far-end SRAM array issue 28 
2 Forward body bias 30 
3 Forward body bias on SRAM cell 32 
4 Partial FBB SRAM array 37 
5 FBB assessment 39 
6 Multi FBB split optimization 44 
7 Simulation result 57 
Chapter 5 Conclusions and future work 63 
1 Conclusions 63 
2 Future work 65 
References 66 
                                

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