一個利用多位元量化器之離散時間2-2強健式雜訊塑型三角積分調變器

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研究生：	王聖琮 Wang, Sheng-Tsung
論文名稱：	一個利用多位元量化器之離散時間2-2強健式雜訊塑型三角積分調變器 A Discrete-Time 2-2 Sturdy-MASH Delta-Sigma Modulator with a Multi-bit Quantizer
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:	許雲翔張順志 Chang, Soon-Jyh 謝秉璇 Hsieh, Ping-Hsuan
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2018
畢業學年度：	106
語文別：	英文
論文頁數：	64
中文關鍵詞：	強健式雜訊塑型、多位元量化器、三角積分調變器
外文關鍵詞：	Sturdy MASH, Multi-bit quantizer, Delta-Sigma Modulator
相關次數：	點閱：2 下載：0
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本文提出一個離散時間之強健式雜訊塑型三角積分調變器，有四階雜訊塑型的效果，能大幅降低的量化雜訊。
所提出的三角積分調變器，利用多迴路系統改善穩定度的問題，如此可以有較好的雜訊塑型效果，以降低量化雜訊並提升效能。迴路系統分為兩級，每一級之迴路濾波器皆為二階，整體系統之迴路濾波器等效為四階，而其每一迴路僅需達到二階迴路濾波器之穩定度需求即可。此外，不同於多級雜訊塑型架構，強健式多級雜訊塑型架構不會有雜訊洩漏導致SNDR降低的問題。此調變器選擇輸入前饋的架構來實現迴路濾波器，如此降低迴路濾波器在內部訊號的大小；並且利用多位元量化器，除了能壓低量化雜訊以達到較好的效能外，也能改善系統穩定度的問題，且能減緩迴路濾波器之線性度需求。在使用強健式雜訊塑型的架構下，此離散時間三角積分調變器的設計能完全消除前級量化雜訊的設計，並提出一改良積分器以降低放大器的規格需求。
此架構使用90奈米1P6M CMOS製程，在1.042-MHz訊號頻寬及25-MHz取樣頻率之下達到62.2-dB的最高SNDR。此調變器的晶片面積為0.71 um2，並在1伏電源電壓的操作。

This thesis presents a discrete-time sturdy multi-stage noise-shaping (SMASH) delta-sigma modulator with fourth-order noise-shaping effect to reduce the quantization noise obviously.
The proposed delta-sigma modulator is composed of two stages with a second-order loop filter in each stage. Hence, it is equivalent to a fourth-order loop filter, but it just need to satisfy the requirement of a second-order loop-filter stability in each loop. The technique not only improves the issue of stability but also achieves more aggressive noise shaping to reduce the in-band quantization noise. In contrast with a multi-stage noise-shaping (MASH) structure, a SMASH one does not suffer from the problem of quantization noise leakage which degrades performance of a delta-sigma modulator. In this proposed modulator, loop filters are implemented by an input-feedforward topology which causes internal nodes lower voltage swings. In addition to reducing quantization noise, it can improve a problem of system stability and relax the requirement on linearity of loop filters by using multi-bit quantizers. In the discrete-time sigma-delta modulator, canceling of the former quantization noise is realized with a SMASH structure, and a modified integrator is proposed to release requirements of opamp specifications.
The prototype is implemented in 90nm 1P9M CMOS technology, achieving 70-dB peak SNDR over a 10-MHz signal bandwidth at a 240-MHz sampling frequency. The modulator occupies 0.71-um2 core area.

ABSTRACT    II
CONTENTS    III
LIST OF FIGURES    VI
LIST OF TABLES    IX
CHAPTER 1    INTRODUCTION    1
1    MOTIVATION    1
2    THESIS CONTRIBUTION    3
3    THESIS ORGANIZATION    4
CHAPTER 2    BACKGROUND INFORMATION    6
1    TOPOLOGY OF ΔΣ MODULATOR    7
1.1    Single-Loop Single-Bit ΔΣ Modulator    8
1.1.1    Cascade of Integrators with Distributed Feedback (CIFB)    9
1.1.2    Cascade of Integrators with Distributed Feedforward (CIFF)    10
1.1.3    Cascade of Resonators with Distributed Feedforward (CRFF)    13
1.2    Single-Loop Multi-Bit ΔΣ Modulator    15
1.3    Multi-Stage Noise-Shaping (MASH) ΔΣ Modulator    17
1.4    Sturdy-MASH (SMASH) ΔΣ Modulator    20
2    SWITCHED-CAPACITOR INTEGRATOR    23
3    SUMMARY    24
CHAPTER 3    SYSTEM-LEVEL DESIGN CONSIDERATIONS    25
1    ARCHITECTURE SELECTION    25
2    SIGNAL TRANSFER FUNCTION (STF)    25
3    TOPOLOGY SELECTION    26
4    NOISE TRANSFER FUNCTION (NTF)    27
5    GAIN FACTOR    28
6    NON-IDEALITIES    29
6.1    kT/C Noise    29
6.2    Thermal Noise of Opamps    31
6.3    Clock jitter    31
6.4    Finite Gain of Opamps    32
6.5    Finite Bandwidth of Opamps    33
6.6    Mismatch of Capacitors    35
7    SUMMARY    36
CHAPTER 4    PROPOSED ΔΣ MODULATOR DESIGN    37
1    PING-PONG INTEGRATOR    37
2    OPERATIONAL AMPLIFIER    38
3    SUMMING CIRCUIT    41
4    QUANTIZER    42
5    DIGITAL CIRCUITS    43
5.1    Non-overlapping Clock Generator    43
5.2    Clock Divider    43
6    CIRCUIT-LEVEL ARCHITECTURE    44
7    SIMULATION RESULTS    47
7.1    Opamps    47
7.2    Quantizers    48
7.3    ΔΣ Modulator    49
8    SUMMARY    51
CHAPTER 5    CHIP IMPLEMENTATION AND MEASUREMENT    52
1    CHIP IMPLEMENTATION    52
2    MEASUREMENT ENVIRONMENT SETUP    53
3    MEASUREMENT RESULTS    54
4    PERFORMANCE SUMMARY AND COMPARISON    56
5    SUMMARY    57
CHAPTER 6    CONCLUSIONS    58
1    SUMMARY    58
2    FUTURE WORK    59

                                

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