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研究生： 江御綸
Chiang, Yu-Lun
論文名稱： 基於數位控制振盪器設計之展頻時脈產生器
A Spread Spectrum Clock Generation using Digital-Controlled Oscillator
指導教授： 黃柏鈞
Huang, Po-Chiun
口試委員: 郭建男
Kuo, Chien-Nan
謝秉璇
Hsieh, Ping-Hsuan
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2025
畢業學年度： 113
語文別： 中文
論文頁數： 26
中文關鍵詞： 全數位 、鎖相迴路 、展頻時脈產生器
外文關鍵詞： ALL-Digital, PLL, SSCG
相關次數： 點閱：2  下載：0 
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    • 近年來因為積體電路製程的迅速發展，處理器內所需的時脈訊號變得越來越龐大，積體電路架構內，因為同時大量的時脈轉換，而導致雜訊影響了電路特性，因此使用展頻時脈技術，降低產品本身所產生的電磁干擾。利用訊號經過展頻分散到更寬的頻帶上，不僅可抑制時脈的基波振盪頻率單一能量，對降低高階諧波峰值也有效。
    目前多數可見的展頻時脈，都是使用壓控振盪電路，搭配展頻技術組合成展頻時脈產生器，為最大化數位操作，得到強健的操作特性，與可能的自動化設計，我們提出了使用數位控制振盪器(DCO)的展頻時脈產生器。利用0.18µm CMOS製程，產生時脈速度400MHz (經由除頻也同時產生200MHz及100MHz之時脈)。在不同製程偏移條件下，中心擴展範圍為(2.19±0.1)%。本作品希望能在簡易的架構下，也能實現良好的展頻時脈，並使結構設計變得更為方便簡單。

    In recent years, the chip with highly integrated circuits suffers from severe spurs due to the large number of clock activities. Spread Spectrum Clock (SSC) technology is used to reduce the electromagnetic interference (EMI) especially for high-speed synchronous digital operation. By spreading the clock signal over a certain of frequency range, the emission energy at the fundamental and the harmonics of clock frequency can be suppressed.
    There are different ways to achieve the spread spectrum clock generator (SSCG). In this work we use the digital-based approaches for its simple circuit architecture and easy for process migration. The design uses a 0.18µm CMOS process. The 400MHz clock cycle is divided to 200MHz and 100MHz clocks. The spread range is (2.19±0.1)% under process corner variations. The proposed structure can fully enjoy the device scaling advantage and efficient design cycle of the digital design flow.

    摘要----------------------------------- i Abstract------------------------------- ii 致謝----------------------------------- iv 目錄----------------------------------- vi 圖目錄---------------------------------- viii 表目錄---------------------------------- x 第一章 緒論----------------------------- 1 1.1 動機與目標-------------------------- 1 1.1.1 研究動機-------------------------- 1 1.1.2 研究目標-------------------------- 1 1.2 內容大綱---------------------------- 2 第二章 背景與相關研究-------------------- 3 2.1 鎖相迴路---------------------------- 3 2.1.1 整數型鎖相迴路-------------------- 3 2.2 展頻時脈---------------------------- 4 2.2.1 展頻技術分類---------------------- 5 2.2.2 非整數型除頻器-------------------- 6 2.2.3 三角積分調變器-------------------- 6 第三章 電路設計------------------------- 8 3.1 電路結構---------------------------- 8 3.1.1 整體電路概略---------------------- 8 3.1.2 相位偵測電路(PD)------------------ 8 3.1.3 Continuous Tuning Stage (CTS)---- 11 3.1.4 展頻時脈控制電路------------------ 16 第四章 實驗結果------------------------- 19 4.1 模擬環境---------------------------- 19 4.2 模擬測試結果與分析------------------- 19 第五章 結論與未來目標-------------------- 24 5.1 結論------------------------------- 24 5.2 未來目標---------------------------- 24 參考文獻 --------------------------------25

    [1] Y.-B. Hsieh and Y.-H. Kao, “A Spread Spectrum Clock Generator Using Fractional-N PLL with an Extended Range Σ∆ Modulator,” IEICE Trans. Electron., vol. E-89C, pp. 851-857, 2006.
    [2] C.-S. Hwang, H.-C. Li, and H.-W. Tsao “A Spread Spectrum Clock Generator Using Digital Modulation Scheme,” IEEE International SOC Conference, 2008.
    [3] P.-C. Huang and S.-Y. Huang, “Cell-Based Delay Locked Loop Compiler,” in Proc. Int. SoC Design Conf. (ISOCC), pp. 91–92. 2016.
    [4] K.-H. Cheng, C.-L. Hung, and Y.-L. Lo, “A Spread Spectrum Clock Generator Using Fractional-N PLL Controlled Delta Sigma Modulator for Serial-ATA III,” IEEE Design and Diagnostics of Electronic Circuits and System, pp. 1-4, 2008.
    [5] H.-H. Chang, I.-H. Hua, and S.-I. Liu, “A Spread-Spectrum Clock Generator with Triangular Modulation,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 673–676, 2003.
    [6] J. Kim and P. Jun, “Dithered Timing Spread Spectrum Clock Generation for Reduction of Electromagnetic Radiated Emission for High-Speed Digital System,” IEEE International Symposium on Electromagnetic Compatibility, vol. 1, pp. 413–418, 2002.
    [7] M. Kokubo et al., “Spread-Spectrum Clock Generator for Serial ATA Using Fractional PLL Controlled by Delta-Sigma Modulator with Level Shifter,” in Proc. IEEE Int. Dig. Tech. Papers. Solid-State Circuits Conf., vol. 1, pp. 160–590, 2005.
    [8] S. Lin and S. Liu, "A 1.5 GHz All-Digital Spread-Spectrum Clock Generator," in IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3111-3119, 2009.
    [9] D. Sheng, C.-C. Chung, and C.-Y. Lee, “An All-Digital Spread Spectrum Clock Generator with Programmable Spread Ratio for SoC Applications,” in Proc. IEEE Asia Pacific Conf. Circuits Systems, pp. 850–853, 2008.
    [10] C.-C Chung, S. Duo and W.-D. Ho. “A Low-Cost Low-Power All Digital Spread-Spectrum Clock Generator,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 5, pp. 983-987, 2015.
    [11] S. Damphousse, K. Ouici, A. Rizki, and M. Mallinson, “All Digital Spread Spectrum Clock Generator for EMI Reduction,” IEEE J. Solid-State Circuits, vol. 42, pp. 145-150, 2007.
    [12] Y. -B. Hsieh and Y. -H. Kao, “A Fully Integrated Spread-Spectrum Clock Generator by Using Direct VCO Modulation,” IEEE Transactions on Circuits and Systems I:Regular Papers, vol. 55, no. 7, pp. 1845-1853, 2008.

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