隨著製程的進步，單位元件尺寸而此不斷的縮小。然而global interconnection沒有隨著製程的進步而跟著縮小而成為performance的瓶頸。Through-Silicon-Via(TSV)由於有低電阻、高電容、高電流傳導能力和好的溫度傳導能力因此成為3D製程整合中最有希望的一個。在傳統的2D設計流程中power network建立的目的是在傳送電流和減少IR drop。然而2D的設計方法由於在3D會有不同的考量因此不能直接應用在3D上。在3D IC中由於層數變多Power密度的上升因此溫度成為了一個重要的議題。此篇paper將在3D IC上利用TSV發展一個Power Distributed Network(STPN)目的在傳送電流減少IR drop、溫度、power noise。然而也會幫助減緩I/O power pin的個數限制。此篇paper將整合3D B*-tree floorplan、電阻power network mesh、溫度power network mesh，並以Simulated Annealing(SA)為演算法來探索floorplan和power network。並且STND會在所選擇的MCNC的benchmark模擬並且結果顯示出3D floorplan、IR drop、power noise、溫度的結果。

[1] P. Falkenstern, Yuan Xie, Yao-Wen Chang, and Yu Wang, \Three-dimensional inte-
grated circuits (3D IC)
oorplan and power/ground network co-synthesis", in Design
Automation Conference (ASP-DAC), 2010 15th Asia and South Pacic, Jan. 2010, pp.
169-174.
[2] William Chen, W. R. Bottoms, Klaus Pressel, and Juergen Wolf, \The next step in
assembly and packaging: System level integration in the package (SiP)", Tech. Rep.,
2008.
[3] Mitsuo Umemoto, Kazumasa Tanida, Yoshihiko Nemoto, Masataka Hoshino, Kazumi
Kojima, Yuji Shirai, and Kenji Takahashi, \High-performance vertical interconnection
for high-density 3D chip stacking package", in Proc. Electronic Components and tech-
nology Conference ECTC, 2004, pp. 616-623.
[4] S.S. Sapatnekar, \Addressing thermal and power delivery bottlenecks in 3D circuits",
in Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacic, Jan.
2009, pp. 423-428.
[5] Hsien-Te Chen, New Architecture of ECO cells, Thermal Sensor and Power Network for
IC Design, PhD thesis, National Tsing Hua University, HsinChu, Taiwan, July 2010.
[6] Chen-Wei Liu and Yao-Wen Chang., \Floorplan and power/ground network co-synthesis
for fast design convergence", in Proceedings of international symposium on Physical
design, 2006, pp. 86 - 93.
[7] Joanna Ho Hao Yu, , and Lei He., \Simultaneous power and thermal integrity driven
via stapling in 3d ics", in Proceedings of International Conference on CAD, 2006, pp.
802 - 808.
[8] Yann Guillou, \3D integration for wireless products: An industrial perspective", Jun.
2009.
[9] M. Koyanagi, T. Fukushima, and T. Tanaka, \Three-dimensional integration technology
and integrated systems", in Design Automation Conference, 2009. ASP-DAC 2009. Asia
and South Pacic, Jan. 2009, pp. 409-415.
[10] B. Goplen and S. Sapatnekar, ", in Physical Design (ISPD.
[11] J. Cong and Y. Zhang., \Thermal via planning for 3d ics", in Computer Aided De-
sign(ICCAD), 2005.
[12] Young-Joon Lee, Yoon Jo Kim, Gang Huang, M. Bakir, Y. Joshi, A. Fedorov, and
Sung Kyu Lim, \Co-design of signal, power, and thermal distribution networks for 3D
ICs", in Design, Automation Test in Europe Conference Exhibition, 2009. DATE '09.,
Apr. 2009, pp. 610-615.
[13] Gang Huang, M. Bakir, A. Naeemi, H. Chen, and J.D. Meindl, \Power delivery for 3d
chip stacks: Physical modeling and design implication", in Electrical Performance of
Electronic Packaging, 2007 IEEE, Oct. 2007, pp. 205 {208.
[14] HSPICE Simulation and Analysis User Guide, V-2004.03, Synopsys, 2004.
[15] Haihua Su, S.S. Sapatnekar, and S.R. Nassif, \Optimal decoupling capacitor sizing
and placement for standard-cell layout designs", Computer-Aided Design of Integrated
Circuits and Systems, IEEE Transactions on, vol. 22, no. 4, pp. 428 - 436, Apr 2003.
[16] Hung-Lung Lin, \A Multiple Power Domain Floorplanning in 3D IC", Master's thesis,
National Tsing Hua University, HsinChu, Taiwan, July 2010.