隨著半導體產業發展使矽電晶體的尺寸縮小已到限制，所以勢必要引入新的材料或創新的結構。由於鍺有比矽高的電子和電洞遷移率，所以被用來作為電晶體的通道材料。為了提升鍺電晶體元件的特性，有一層高品質的界面層是需要的。因此提供一個精確和快速的量測方法去偵測界面缺陷密度和深層缺陷是值得研究的主題。本論文以電荷汲引原理為基礎，提出了多種量測技術用來探測缺陷密度分佈。
第一部分為界面層氫處理與微波退火電晶體元件，可以得到經過氫處理和微波退火的元件，具有較低的界面缺陷密度，較好的界面層品質。電性上有較大的驅動電流和較低的關閉電流，在載子遷移率上也有更好的表現。而邊緣陷阱縱深分佈上，氫處理可以有效的改善縱深小於0.8 nm缺陷密度；而微波退火可以顯著的改善縱深大於1 nm的缺陷密度。
第二部分為利用電荷汲引技術去比較不同的介電層ZrO2和HfON電晶體的界面缺陷密度、邊緣陷阱密度、和應力誘發缺陷的增生。結果顯示了ZrO2元件有較高的界面缺陷密度但有較低的邊緣缺陷密度；HfON元件有較低的界面缺陷密度但有較高的邊緣缺陷密度。說明了ZrO2元件在可靠度分析上，能抑制電荷在介電層被捕捉，主要是因為具有較低的邊緣缺陷密度所致。
第三部分為利用電荷汲引技術去量測有無Hf緩衝層電晶體的界面缺陷密度、邊緣陷阱密度、和應力誘發缺陷的增生。經電荷汲引技術來看可發現有Hf緩衝層的元件，有較低界面陷阱密度和邊緣陷阱密度，得到有較佳的界面品質和介電層，而電性上也都有改善。經由NBTI和PBTI可靠度分析，從電荷汲引技術發現NBTI對界面層的破壞較嚴重；而PBTI則是在介電層有嚴重的破壞，發現有Hf緩衝層元件都有較好的表現，主要是有較好的界面層和介電層品質。

As the scaling of silicon metal-oxide-semiconductor (MOSFET) approach to its limitation with the development of semiconductor industry, novel materials and innovative device structures need to be introduced in future. Ge is promising for a channel material in MOSFET, owing to its high hole and electron mobility. A high quality interface layer is necessary to improve characteristics on Ge-MOSFETs device. Hence, an accurate and quick measurement to detect interface trap density and distribution of bulk traps should be a valuable research topic. Several measurement techniques based on the charge pumping are proposed to detect trap density distributions.
In the first study, interface layer with hydrogen treatment and microwave annealing Ge MOSFET devices obtain lower interface trap density and better interface layer quality than without one. The electrical characteristic have higher drive current, mobility, and lower off current, due to interface layer with hydrogen treatment can repair interface traps and microwave annealing can improve PN junction. On the other hand, hydrogen treatment can improve traps density less than depth about 0.8 nm and microwave annealing can obviously reduce traps density higher than depth about 1 nm from distribution profile of border traps density.
In the second study, the interface trap density, bulk density and stress induced trap generation of Ge-pMOSFETs with ZrO2 and HfON gate dielectrics are extracted and compared by CP technique. Results show that ZrO2 device has higher interface trap density but lower bulk trap density than HfON device, which implies that ZrO2 device has inferior Ge/dielectric interface but high quality dielectric bulk. The improved reliability characteristics in ZrO2 device can be attributed to the low preexisting bulk trap density which suppresses charge trapping in the dielectric bulk.
In the last study, charge pumping technique is used to detect interface and bulk trap distribution and stress induced trap generation of Ge-pMOSFETs with and without Hf buffer layer (HBL). The charge pumping technique confirm that device with HBL has lower interface and bulk traps density than device without, which show electrical characteristic can be improved. Results show that device with HBL has better performance from NBTI and PBTI reliability analysis because of it has higher quality of interface characteristics and dielectric bulk.

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