研究生: |
楊之佳 Chih-Chia Yang |
---|---|
論文名稱: |
低功率快閃記憶體讀取字線電壓產生器 Low power FLASH memory read word-line voltage generator |
指導教授: |
連振炘
Chen-Hsin Lien |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2006 |
畢業學年度: | 94 |
語文別: | 英文 |
論文頁數: | 66 |
中文關鍵詞: | 快閃記憶體 、電壓產生器 、低功率 、字線 |
外文關鍵詞: | FLASH memory, voltage generator, low power, word-line |
相關次數: | 點閱:1 下載:0 |
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本篇論文探討了快閃記憶體在讀寫時的字線電壓產生器。
首先,本論文討論了快閃記憶體的讀取操作。在讀取時,元件電流不可過小。在元件尺寸越來越小的今天,傳統使用工作電壓作為讀取字線電壓的方法已不足以供給合理的元件電流。因此,字線電壓產生器將越來越形重要。更進一步,經由模擬可以得知,在溫度較高時使用較高的字線電壓,可以得到較一致的元件電流。
接下來討論並比較了兩種不同的字線電壓產生方法:瞬升壓法(kick method)和池壓方法(pool method)。瞬升壓法的主要優點是不消耗靜態功率。池壓方法雖然會消耗靜態功率,但速度較快,且輸出電壓較易調整。
由於速度的考量,我們進一步研究池壓方法電路。為解決靜態高功率問題,我將原件偏壓在弱反轉區域。這一方法有效地降低了靜態功率,但相對的電路所消耗的面積會相當大。
As supply voltage becomes lower and lower, the read word-line voltage generator becomes more and more important. In this thesis, the word-line voltage generator for FLASH memory read operation is studied.
First, the requirement of read word-line voltage is studied. It appears that the read word-line voltage could not be too low for cell current concern. Thus, the supply voltage is no longer suitable as device scales down. However, the word-line voltage could not be too high either, for cell current ratio concern. Moreover, the relation of cell current and temperature is also studied. For cell current consideration, the word-line voltage should be higher at high temperature.
Two kinds of read word-line voltage generator are then compared. The kick method is superior for its low stand-by power. The pool method, on the contrary, has better speed and accuracy. To obtain fast access time, the pool method is further implemented. The high stand-by power of pool method is solved by biasing the devices in weak inversion.
The simulation result shows that the utilization of weak inversed devices indeed suppresses stand-by power. However, area now becomes the main cost of this method.
[1] Introduction to flash memory, Bez, R.; Camerlenghi, E.; Modelli, A.; Visconti, A.; Proceedings of the IEEE, Volume 91, Issue 4, April 2003 Page(s):489 – 502, Digital Object Identifier 10.1109/JPROC.2003.811702
[2] http://home.businesswire.com/
[3] The flash memory read path: building blocks and critical aspects, Micheloni, R.; Crippa, L.; Sangalli, M.; Campardo, G.;Proceedings of the IEEE, Volume 91, Issue 4, April 2003 Page(s):537 – 553, Digital Object Identifier 10.1109/JPROC.2003.811704
[4] Optimization of word-line booster circuits for low-voltage flash memories, Tanzawa, T.; Atsumi, S.; Solid-State Circuits, IEEE Journal of, Volume 34, Issue 8, Aug. 1999 Page(s):1091 – 1098, Digital Object Identifier 10.1109/4.777107
[5] Wordline voltage generating system for low-power low-voltage flash memories, Tanzawa, T.; Umezawa, A.; Kuriyama, M.; Taura, T.; Banba, H.; Miyaba, T.; Shiga, H.; Takano, Y.; Atsumi, S.; Solid-State Circuits, IEEE Journal of Volume 36, Issue 1, Jan. 2001 Page(s):55 – 63, Digital Object Identifier 10.1109/4.896229
[6] On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique, Dickson, J.F.; Solid-State Circuits, IEEE Journal of, Volume 11, Issue 3, Jun 1976 Page(s):374 - 378
[7] A dynamic analysis of the Dickson charge pump circuit, Tanzawa, T.; Tanaka, T.; Solid-State Circuits, IEEE Journal of Volume 32, Issue 8, Aug. 1997 Page(s):1231 – 1240, Digital Object Identifier 10.1109/4.604079
[8] Dynamic analysis of Dickson charge pump circuits with a resistive load, Zhang, M.; Llaser, N.; Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 10th IEEE International Conference on, Volume 2, 14-17 Dec. 2003 Page(s):431 - 434 Vol.2, Digital Object Identifier 10.1109/ICECS.2003.1301814
[9] A CMOS bandgap reference circuit with sub-1-V operation, Banba, H.; Shiga, H.; Umezawa, A.; Miyaba, T.; Tanzawa, T.; Atsumi, S.; Sakui, K.; Solid-State Circuits, IEEE Journal of, Volume 34, Issue 5, May 1999 Page(s):670 – 674, Digital Object Identifier 10.1109/4.760378
[10] Using the weak inversion region to optimize input stage design of CMOS op amps, Comer, D.J.; Comer, D.T.;Circuits and Systems II: Express Briefs, IEEE Transactions on [see also Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on], Volume 51, Issue 1, Jan 2004 Page(s):8 – 14, Digital Object Identifier 10.1109/TCSII.2003.821517