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研究生: 張 延
Chang, Yan
論文名稱: 電漿處理在金屬-絕緣層-N型鍺接觸的影響研究
Effects of Plasma Treatment on Metal/Insulator/n-type Germanium Contact
指導教授: 吳文發
Wu, Wen-Fa
張廖貴術
ChangLiao, Kuei-Shu
口試委員: 吳永俊
Wu, Yung-Chun
羅廣禮
Luo, Guang-Li
學位類別: 碩士
Master
系所名稱: 原子科學院 - 工程與系統科學系
Department of Engineering and System Science
論文出版年: 2019
畢業學年度: 108
語文別: 中文
論文頁數: 69
中文關鍵詞: 電漿處理接觸
外文關鍵詞: plasma, germanium, contact
相關次數: 點閱:3下載:0
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  • 鍺是近幾年極受矚目的半導體元件通道材料,擁有比矽材料更高的載子遷移率,但是在N型Ge通道金屬氧化物半導體場效電晶體(MOSFET)的發展中存在著許多障礙,特別是在源極/汲極(S/D)會因為費米能階釘紮(Fermi-level pinning)的現象形成高接觸電阻值。而造成費米能階釘紮的原因是金屬與半導體接觸面太多缺陷和金屬所導致的能隙能階(MIGS)所導致。本論文是以N型Ge基板與金屬的接面做介面工程,使其介面處的缺陷減少和MIGS效應得到緩解,並進一步降低費米能階釘紮的效應而得到較低的接觸電阻值,探討其提升的元件電特性。
    第一部分先使用蝕刻機台的SF6電漿在Ge的表面形成一層修補缺陷的鈍化層(passivation),藉由改變電漿作用的時間來找出最有效的鈍化層。在經10秒的SF6電漿處理後,XPS分析發現表面的S與F元素含量分別為7.52% 與0.69%,可得到最佳接觸電阻值為3.10*10-4 Ω*cm2。另外再使用ALD沉積的TiO2氧化層做為介面層,其中分別使用不同cycle數使得介面層的厚度改變,分別為1.57nm、2.25nm、5.19nm。最佳的厚度為2.25nm作為元件的介面層,得到的接觸電阻值為2.30*10-5 Ω*cm2。最終結合兩者最佳的參數,先在Ge基板表面進行SF6電漿處理而後再沉積TiO2氧化層,但最後量測出來的結果與預期不同,從TEM和AFM看出是因為經過SF6電漿處理後Ge的表面因為蝕刻關係變得相當粗糙,接續沉積的TiO2介面氧化層反而無法有效的形成,缺陷也提高許多造成電性變得很差。
    第二部分採用第一部分最佳的TiO2氧化層厚度,對其做NH3電漿處理,目的為增加TiO2氧化層中的氧空缺含量以及氮化TiO2氧化層,使其氧化層的導電性增加且進一步降低接觸電阻。實驗首先在TiO2氧化層表面做NH3電漿處理60秒,因考量氮化後TiO2氧化層會改變,故在參數上以調變TiO2氧化層厚度搭配有無使用NH3電漿處理做比對,結果從電性上發現變化不大,故在後續實驗中設計在TiO2氧化層中做均勻的混合處理,除了能使NH3電漿均勻的與TiO2氧化層完整反應,也能使氫原子鈍化TiO2/Ge介面,藉由沉積1 cycle的TiO2後進行5秒的NH3電漿處理為一個循環,連續進行12次循環後,再進行88次單純沉積循環的ALD TiO2氧化層沉積(MIX),雖然分析後得到在TiO2氧化層變厚為2.94nm,但若有經過MIX方式的NH3電漿均勻處理仍能使逆偏電流密度值再提升0.5order,接觸電阻值為5.24*10-4 Ω*cm2,從以上的實驗得知在均勻混合的TiO2氧化層以及NH3電漿處理後能使得逆偏電流密度有效的提升,未來若能更有效的控制TiO2氧化層經NH3電漿處理後的厚度,預期能使得電性上能有再進一步的提升。


    Germanium is regarded as a promising channel material owing to higher carrier mobility in recent years. However, there are many problems in the development of N-type Ge MOSFET. A high resistance contact was formed at the interface between source/drain(S/D) and metal due to the Fermi-level pinning, which caused by many defects in the metal-semiconductor contact surface and the metal-induced gap states (MIGS). In this thesis, the effects of plasma treatment on M-I-S contact structure are investigated by interface engineering between N-type Ge wafer and metal. A lower contact resistance can be achieved by reducing the defects at the interface and the MIGS effect.
    In the first part, the SF6 plasma treatment was used to form a passivation layer to repair the defects at the surface of Germanium. To optimize passivation effect, the SF6 plasma treatments were applied for various time. The optimized SF6 plasma treatment time was 10 seconds, and corresponding S and F concentration were 7.52% and 0.69% from XPS analysis. The contact resistance was 3.10*10-4 Ω*cm2. In addition, ALD TiO2 interfacial layer was used to form M-I-S contact structure. TiO2 layers with a thickness of 1.57 nm, 2.25 nm and 5.19 nm were deposited by ALD. The optimum thickness of TiO2 interfacial layer was 2.25 nm and a corresponding contact resistance of 2.30*10-5 Ω*cm2 was obtained. Then both SF6 plasma treatment and TiO2 interfacial layer were applied to improve contact property of the n-Ge device. However, electrical characteristics became worse. The TEM and AFM showed that the Ge surface became rougher after SF6 plasma treatment. As a result, the defects increased and the TiO2 oxide interfacial layer couldn’t be formed effectively.
    In the second part, NH3 plasma treatment was applied to the TiO2 oxide interfacial layer to increase the oxygen vacancy and form TiOxNy. The aforementioned process increased the conductivity of the oxide layer and further reduced the contact resistance. The TiO2 oxide layer was treated by NH3 plasma for 60 seconds. Because the thickness of TiO2 oxide layer might change after the plasma nitridation process, the TiO2 oxide interfacial layers with various thickness were used. However, the electrical properties were similar after the NH3 plasma treatment. Hence, a uniform mixing treatment at TiO2/Ge interface was designed to improve the electrical characteristics. First, a mixing cycle process, which was one cycle TiO2 deposition and following NH3 plasma treatment for 5 seconds, was applied. After repeating this mixing cycle process for 12 times, the TiO2 oxide layer was then deposited by following 88 ALD cycles. The process could also passivate the TiO2/Ge interface by hydrogen. Though the thickness of the resulting oxide interfacial layer increased to 2.94 nm after the uniform mixing treatment, the reverse bias current density increased by 0.5 order, and the contact resistance could reduce to 5.24*10-4 Ω*cm2.
    The reverse bias current density can be effectively improved by the NH3 plasma treatment. The electrical property of Ge M-I-S contact can be further improved by optimizing thickness of the NH3 plasma treated TiO2 oxide interfacial layer.

    摘要 i Abstract iii 致謝 v 目錄 vi 表目錄 ix 圖目錄 x 第一章 序論 1 1.1 前言 1 1.2 使用鍺作為通道材料 1 1.3 源極與汲極在奈米尺度下面臨的問題 2 1.4 N型鍺電晶體接觸電阻降低困難的原因 3 1.4.1 金屬誘導的間隙狀態 4 1.4.2 介面能態 4 1.5 降低鍺接觸電阻的文獻回顧 4 1.5.1 摻雜濃度增加 5 1.5.2 夾層 6 1.5.3 鈍化層 7 1.5.4 氧空缺 8 1.5.5 鍺合金 9 1.6 CTLM量測機制 9 1.7 論文架構 11 第二章 元件製程與量測 26 2.1 實驗製程與原理 26 2.1.1 實驗前晶片清洗 26 2.1.2 以ALD成長TiO2氧化層&濺鍍金屬層 26 2.1.3 電漿原理及應用 27 2.2 電性量測 27 2.3 物性分析 28 2.3.1 原子力顯微鏡AFM 28 2.3.2 穿透式電子顯微鏡 29 2.3.3 X射線光電子能譜儀 29 2.3.4 能量色散X-射線光譜 29 第三章 SF6鈍化層與TiO2氧化層夾層的結合研究 36 3.1 研究動機 36 3.2 製程與條件 36 3.3 實驗結果與討論 37 3.3.1 不同鈍化處理時間對 J-V電性的影響 37 3.3.2 不同TiO2氧化層厚度對J-V電性的影響 39 3.3.3 結合兩製程J-V電性的影響 40 3.4 結論 40 第四章 TiO2氧化層夾層與NH3電漿處理結合應用 53 4.1 研究動機 53 4.2 製程與條件 53 4.3 實驗結果與討論 54 4.3.1 於不同厚度TiO2氧化層表面進行NH3電漿處理 54 4.3.2 在TiO2/Ge介面做NH3電漿處理 55 4.4 結論 57 第五章 結論與展望 64 5.1 結論 64 5.2 未來展望 65 第六章 參考文獻 66

    [1] D.K. Schroder, Semiconductor Material and Device Characterization, 3nd Edition, Wiley, 2006
    [2] W. P. Bai et al., IEEE Electron Device Letters, Vol. 26, p. 378, 2005
    [3] A. Dimoulas, P. Tsipas, A. Sotiropoulos, “Fermi-level pinning and charge neutrality level in germanium,” Applied Physics Letters, Vol. 89, p. 252110, 2006
    [4] K. Kuhn, “22-nm CMOS Technology.”, IEDM Short Course, San Francisco, USA, 2008.
    [5] Kim Young, IEDM Short Course, Washington, USA, 2011
    [6] S.E. Thompson, and S. Parthasarathy, “Moore's law: the future of Si microelectronics,” Materials Today, Vol. 9, pp. 20-25, 2006
    [7] G. Yeric, “Moore's law at 50: Are we planning for retirement,” IEDM Short Course, Washington, USA, p. 60, 2014
    [8] P. Raghavan et al., “Holisitic device exploration for 7nm node,” Custom Integrated Circuits Conference (CICC), San Jose, CA, USA, 2015
    [9] R. Islam, G. Shine, and K.C. Saraswat, “Schottky barrier height reduction for holes by Fermi level depinning using metal/nickel oxide/silicon contacts,” Applied Physics Letters, Vol. 105, p. 182103, 2014
    [10] T. Nishimura, K. Kita, and A. Toriumi, “Evidence for strong Fermi-level pinning due to metal-induced gap states at metal/germanium interface,” Applied Physics Letters, Vol. 91, p. 123123, 2007
    [11] J.R. Weber et al., “Dangling-bond defects and hydrogen passivation in germanium,” Applied Physics Letters, Vol. 91, p. 142101, 2007
    [12] A. Ebong, and N. Chen, “Metallization of crystalline silicon solar cells: A review. in High Capacity Optical Networks and Emerging/Enabling Technologies,” International Symposium on High Capacity Optical Networks and Enabling Technologies, Istanbul, Turkey, 2012
    [13] S. Huang, F. Lu, and C.W. Liu, “Low contact resistivity (1.5×10−8 Ω-cm2) of phosphorus-doped Ge by in-situ chemical vapor deposition doping and laser annealing,” International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, Taiwan, 2016
    [14] C. Hsu et al., “Fabricating a n+-Ge contact with ultralow specific contact resistivity by introducing a PtGe alloy as a contact metal,” Applied Physics Letters, Vol. 107, p. 113503, 2015
    [15] H. Miyoshi et al., “In-situ contact formation for ultra-low contact resistance NiGe using carrier activation enhancement (CAE) techniques for Ge CMOS,” Symposium on VLSI Technology, Honolulu, HI, USA, 2014
    [16] K. Jiseok et al., “Specific contact resistivity of n-type Si and Ge M-S and M-I-S contacts,” Simulation of Semiconductor Processes and Devices (SISPAD), Washington, DC, USA, 2015
    [17] S. Gupta et al., “Contact resistivity reduction through interfacial layer doping in metal-interfacial layer-semiconductor contacts,” Applied Physics Letters, Vol. 113, p. 234505, 2013
    [18] B.Y. Tsui, and M.H. Kao, “Mechanism of Schottky barrier height modulation by thin dielectric insertion on n-type germanium,” Applied Physics Letters, Vol. 103, p. 032104, 2013
    [19] S. Dev et al., “Low resistivity contact on n-type Ge using low work-function Yb with a thin TiO2 interfacial layer,” Applied Physics Letters, Vol. 108, p. 103507, 2016
    [20] A. Agrawal et al., “Fermi level depinning and contact resistivity reduction using a reduced titania interlayer in n-silicon metal-insulator-semiconductor ohmic contacts,” Applied Physics Letters, Vol. 104, p. 112101 2014
    [21] A. Agrawal et al., “Barrier height reduction to 0.15 eV and contact resistivity reduction to 9.1×10−9 Ω-cm-2 using ultrathin TiO2−x interlayer between metal and silicon,” Symposium on VLSI Technology, Kyoto, Japan, 2013
    [22] J.-Y.J. Lin, A.M. Roy, and K.C. Saraswat, “Reduction in Specific Contact Resistivity to n+Ge Using TiO2 Interfacial Layer,” IEEE Electron Device Letters, Vol. 33, pp. 1541-1543, 2012
    [23] G.-S. Kim et al., “Effective Schottky barrier height lowering of metal/n-Ge with a TiO2/GeO2 interlayer stack,” ACS Applied Materials & Interfaces, Vol. 8, pp. 35419-35425, 2016
    [24] J.-Y.J. Lin, A.M. Roy, and K.C. Saraswat, “Reduction in Specific Contact Resistivity to n+Ge Using TiO2 Interfacial Layer,” IEEE Electron Device Letters,. Vol. 33, pp. 1541-1543, 2012
    [25] Y. Seo et al., “Fermi Level Depinning in Ti/GeO2/n-Ge via the Interfacial Reaction Between Ti and GeO2,” IEEE Transactions on Electron Devices, Vol. 64, pp. 4242-4245, 2017
    [26] J.-R. Wu et al., “Impact of fluorine treatment on Fermi level depinning for metal/germanium Schottky junctions,” Applied Physics Letters, Vol. 99, p. 253504, 2011
    [27] G.-S. Kim et al., “Surface passivation of germanium using SF6 plasma to reduce source/drain contact resistance in germanium n-FET,” IEEE Electron Device Letters, Vol. 36, p. 745-747, 2015
    [28] A.V. Thathachary et al., “Fermi level depinning at the germanium Schottky interface through sulfur passivation,” Applied Physics Letters, Vol. 96, p. 152108, 2010
    [29] G.-S. Kim et al., “Specific contact resistivity reduction through Ar plasma-treated TiO2−x interfacial layer to metal/Ge contact,” IEEE Electron Device Letters, Vol. 35, pp. 1076-1078, 2014
    [30] G.-S. Kim et al., “Effect of Hydrogen Annealing on Contact Resistance Reduction of Metal–Interlayer–n-Germanium Source/Drain Structure,” IEEE Electron Device Letters, Vol. 37, pp. 709-712, 2016
    [31] D. Biswas et al., “Enhanced thermal stability of Ti/TiO2/n-Ge contacts through plasma nitridation of TiO2 interfacial layer,” Applied Physics Letters, Vol. 110, p. 052104, 2017
    [32] Z. Li et al., “Study on Schottky barrier modulation of NiGe/Ge by ion-implantation after germanidation technique,” International Conference on Solid-State and Integrated Circuit Technology, Xi'an, China, 2012
    [33] C.-P. Chou, H.-H. Chang, and Y.-H. Wu, “Enabling low contact resistivity on n-Ge by implantation after Ti germanide,” IEEE Electron Device Letters, Vol. 39, pp. 91-94, 2017
    [34] P. Zhang, “Effects of Surface Roughness on Electrical Contact, RF Heating and Field Enhancement,” University of Michigan, Doctor, 2012
    [35] T. Liu et al., “Study on the measurement accuracy of circular transmission line model for low-resistance Ohmic contacts on III-V wide band-gap semiconductors,” Current Applied Physics, Vol. 18, pp. 853-858, 2018
    [36] H. Yu et al., “A simplified method for (circular) transmission line model simulation and ultralow contact resistivity extraction,” IEEE Electron Device Letters, Vol. 35, pp. 957-959, 2014

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