3.3kV級4H碳化矽垂直型金氧半場效電晶體性能及未箝制電感切換模擬研究

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研究生：	林丹晳 Lin, Tan-Hsi
論文名稱：	3.3kV級4H碳化矽垂直型金氧半場效電晶體性能及未箝制電感切換模擬研究 Simulation Study of 3.3-kV-Class 4H-SiC DMOSFET Performance and Unclamped Inductive Switching
指導教授：	黃智方 Huang, Chih-Fang
口試委員:	李傳英吳添立
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2018
畢業學年度：	106
語文別：	中文
論文頁數：	59
中文關鍵詞：	3.3kV 、碳化矽、垂直型金氧半場效電晶體、未箝制電感切換模擬
外文關鍵詞：	3.3kV, Silicon Carbide, DMOSFET, Unclamped Inductive Switching Simulation
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本論文分成兩部份，第一部份包含將反摻雜接面終結延伸 (CD-JTE) 應用於3.3kV級碳化矽金氧半場效電晶體之設計以及反向、順向特性之優化。在反向特性上，藉由反摻雜N型元素於P型JTE創造出多區段的效果，提升元件崩潰電壓。在順向特性上，藉由調整JFET區域寬度、電流散佈層、以及JFET區域摻雜等參數，可以將特徵導通電阻優化。根據量測結果，崩潰電壓達到90%的理想崩潰電壓，而特徵導通電阻值為13 mohm-cm2。
第二部分為未箝制電感切換 (UIS) 作用於碳化矽金氧半場效電晶體之探討，將介紹其測試目的以及原理，並且討論其失效機制。為了模擬之收斂以及符合量測資料，更改了元件之規格、結構、以及游離碰撞參數。由模擬結果得知，元件電流為11.8 A時，UIS測試失效，此時臨界溫度為1450 K。失效原因根據崩潰電流路徑，歸因於高溫時造成的閾值電壓下降。

This thesis is divided into two parts. The first part includes the design of counter-doped junction termination extension (CD-JTE) for a 3.3kV SiC DMOSFET and the optimization of its reverse and forward characteristics. On the reverse characteristics, by counter-implantation of N-type species into P-type JTE to create a multi-zone effect, the breakdown voltage of the device is increased. On the forward characteristics, by adjusting the JFET width, current spreading layer, and JFET implant parameters, the specific on-resistance can be optimized. According to the measurement results, the breakdown voltage reaches 90% of the ideal breakdown voltage, and the value of specific on resistance is 13 mohm-cm2.
The second part is the discussion of SiC DMOSFETs under Unclamped Inductive Switching (UIS). The test purpose and principle is introduced, and then the failure mechanism is discussed. For the convergence in simulation and to fit the measurement data, the device specification, structure, and impact ionization parameter has been adjusted accordingly. From the simulation results, device fails the UIS test at 11.8 A current when the critical temperature is 1450 K. The reason of failure is attributed to the decrease of threshold voltage at a high temperature, determined by the path of avalanche current.

中文摘要..............................................I
Abstract............................................II
致謝................................................IV
目錄................................................VI
圖目錄..............................................VIII
表目錄...............................................XI
第一章 序論..........................................1
1.1 碳化矽材料簡介....................................1
1.2 垂直型雙佈植金氧半場效電晶體.......................1
1.3 文獻回顧.........................................3
1.3.1 邊緣終結防護結構(Edge Termination)..............3
1.3.2 未箝制電感切換(Unclamped Inductive Switching)...4
1.4 研究動機與論文大綱................................7
第二章 元件主動區與邊緣防護區之設計與實際量測............8
2.1 漂移層參數選定....................................8
2.2 DMOS參數選定.....................................10
2.2.1 JFET區域寬度調變...............................10
2.2.2 電流散佈層(Current Spreading Layer)調變.........12
2.2.3 JFET區域N型摻雜調變.............................13
2.3 接面終結延伸設計..................................15
2.4 實際製程元件量測結果...............................20
第三章 DMOS未箝制電感切換模擬與討論.....................27
3.1 元件UIS測試失效機制討論............................27
3.1.1 本質載子濃度上升................................27
3.1.2 寄生雙極性電晶體開啟.............................28
3.1.3 閾值電壓下降....................................29
3.2 一維熱傳導模型之近似...............................29
3.3 DMOS元件結構以及游離參數模型調整...................33
3.4 UIS測試模擬結果與討論.............................36
第四章 結論以及未來展望................................55
參考文獻..............................................56


                                

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