適用於多輸入多輸出通訊系統之高傳輸率低複雜度軟性輸出球體解碼器

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研究生：	王曉淇 Wang, Hsiao-Chi
論文名稱：	適用於多輸入多輸出通訊系統之高傳輸率低複雜度軟性輸出球體解碼器 A High Throughput Low Complexity Soft-output Sphere Decoder for MIMO Communications
指導教授：	馬席彬 Ma, Hsi-Pin
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	67
中文關鍵詞：	多輸入多輸出、球體解碼器
外文關鍵詞：	MIMO, Sphere Decoder
相關次數：	點閱：3 下載：0
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在這篇論文裡，我們推薦了一個具有高輸出率、固定複雜度的軟性輸出球體解碼器，並支援QPSK、16-QAM、64-QAM調變的4x4多輸入多輸出通訊系統。

為了達到軟性輸出，本論文提出了特定的搜尋樹演算法。隨著一些模擬的數據結果，可以修改原始硬性輸出的固定式球體解碼器(Fixed-complexity Sphere Decoder, FSD)的搜尋樹而成為具有軟性輸出的搜尋樹。和理想的球體解碼器相比，所提出的軟性輸出固定複雜度球體解碼器(Soft-output FSD, SFSD)有少許訊框錯誤率表現上的衰退(0.5dB)，但是得到的好處是得到固定的運算複雜度還有更適合用平行或是管線(pipeline)的硬體架構來實現。

除此之外，一個高傳輸率的硬體架構被提出來實現SFSD的演算法。球體解碼器的列舉部分透過一些設計來達到簡化。平行的硬體架構被採用來達成高傳輸率。許多的管線電路也被適當的插入硬體架構之中以達到高的運作時脈。這些設計都被採用來達成高傳輸率同時降低複雜度的目的。

最後，電路使用台積電的0.18um的製程和本實驗室特有的元件資料庫(Cell Library)進行合成。在經過合成後，所提出的硬體架構面積大約有100k的等效邏輯閘面積。等效的邏輯閘是最基本的NAND邏輯閘。最快傳輸率在16-QAM調變的時候可以達到120Mbps。而FPGA的擬真也同樣的完成以達到驗證所設計的電路是否真的能使用。於是一個高解碼表現、高傳輸率的軟性輸出MIMO偵測器完整的從本論文中提出。

In this thesis, a high throughput fixed complexity soft-output sphere decoder supporting QPSK, 16-QAM, and 64-QAM modulation in the 4x4 MIMO system is proposed.

For achieving soft-output, the proposed tree search algorithm is presented. Some simulation results help to modify the tree search algorithm of the original fixed-complexity sphere decoder (FSD) for soft-output detection. Compared with the optimal soft-output sphere decoder, the proposed soft-output FSD (SFSD) has a little frame error rate (FER) degradation (0.5dB), but the benefit is that SFSD has fixed complexity and can suit to a parallel or full pipeline hardware design.

Moreover, a high throughput hardware architecture is proposed to implement the SFSD algorithm. A simplified enumeration method is proposed to reduce the hardware complexity. The parallel architecture is proposed to achieve high throughput. For the high clock frequency, many pipelines are inserted into the proposed architecture.

In addition, the proposed SFSD is implemented by the 0.18um CMOS cell-library of HP laboratory. The area of proposed hardware implementation is about 100k equivalent gates corresponding to the two-input drive-one NAND gate. The maximum throughput can reach to 120Mbps with 16-QAM modulation. Finally, the FPGA emulation is made to verify the proposed design is able to work. Then a high performance high throughput soft-output MIMO detector has completely accomplished in the thesis.

Introduction 1
1 Overview of Wireless Communication Systems . . . . . . . . . . . . . . . . 1
2 Motivation of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Multiple-Input Multiple-Output (MIMO) Systems 3
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Multiple-Input Multiple-Output . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 MIMO System Model . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Channel Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Categories of MIMO Techniques . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Diversity Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Spatial Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Precoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Hard-Output and Soft-Output . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Turbo-MIMO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 MIMO APP Detection . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Simplification APP Detection . . . . . . . . . . . . . . . . . . . . . 13
Detection for Spatial Multiplexing MIMO Communications 15
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2 Linear Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Zero Forcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Minimum Mean Square Error . . . . . . . . . . . . . . . . . . . . . 16
3 Nonlinear Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Maximum Likelihood . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Ordered Successive Interference Cancelation . . . . . . . . . . . . . 17
4 Sphere Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Sphere Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Tree Pruning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Preprocess with Sort . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5 Categories of Tree Search . . . . . . . . . . . . . . . . . . . . . . . 23
4.6 Soft-Output Sphere Decoder . . . . . . . . . . . . . . . . . . . . . . 26
Soft-Output Fixed Complexity Sphere Decoder 29
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2 System Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3 Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.4 SNR Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3 Soft-Output Fixed-Complexity Sphere Decoder . . . . . . . . . . . . . . . . 32
3.1 Tree Search for Soft-Output . . . . . . . . . . . . . . . . . . . . . . 32
3.2 Modified FSD Algorithm for Soft-Output . . . . . . . . . . . . . . . 35
3.3 Comparison of SFSD Distribution . . . . . . . . . . . . . . . . . . . 36
3.4 Simplified Enumeration for proposed SFSD algorithm . . . . . . . . 38
3.5 Complexity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Hardware Implementation and Measurement 45
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3 Architecture Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.1 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2 Partial Euclidean Distance (PED) Part . . . . . . . . . . . . . . . . . 48
3.3 List Administration Unit (LAU) Part . . . . . . . . . . . . . . . . . . 48
3.4 LLR computation Part . . . . . . . . . . . . . . . . . . . . . . . . . 48
4 Word-Length Determination . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.1 Word-Length Determination Method . . . . . . . . . . . . . . . . . 49
4.2 Simulation Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1 First Partial Euclidean Distance Unit . . . . . . . . . . . . . . . . . . 52
5.2 Partial Euclidean Distance Unit . . . . . . . . . . . . . . . . . . . . 53
5.3 List-Administration Unit . . . . . . . . . . . . . . . . . . . . . . . . 53
5.4 Input Buffer and Output Buffer . . . . . . . . . . . . . . . . . . . . 54
6 FPGA Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7 Complexity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9 MIMO-OFDM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
FutureWorks and Conclusions 61
1 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
FutureWork and Conclusions 63
1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

                                

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