快閃記憶體錯誤診斷與測試時間縮減｜國立清華大學博碩士論文庫

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研究生：	葉人傑 Jen-Chieh Yeh
論文名稱：	快閃記憶體錯誤診斷與測試時間縮減 Flash Memory Fault Diagnostics and Test Time Reduction
指導教授：	吳誠文 Cheng-Wen Wu
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	95
語文別：	英文
論文頁數：	78
中文關鍵詞：	快閃記憶體、測試、錯誤診斷、內建自我診斷、半導體記憶體、測試時間縮減
外文關鍵詞：	Flash Memory, Testing, Fault Diagnosis, Built-In Self-Diagnosis, Semiconductor Memory, Test Time Reduction
相關次數：	點閱：2 下載：0
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隨著快閃記憶體單位密度與記憶容量的快速成長，再加上快閃記憶體冗長地測試時間，使得快閃記憶體測試機台(ATE)更加複雜化。然而，針對測試機台上費時的錯誤診斷流程，更嚴重增加了測試成本與延宕了量產時間，因此有效率的快閃記憶體診斷方法已經是目前刻不容緩的議題。根據我們之前研究開發出系統化之快閃記憶體干擾故障模型與高效率位元與字元之測試演算法(March-like Test Algorithms)，在這次的研究論文中，我們提出了低成本、高效能之快閃記憶體錯誤診斷法。此快閃記憶體錯誤診斷法有效地區分出失敗位元圖(fail bit-maps)中錯誤位元之錯誤行為，利用錯誤特徵(fault signature)與錯誤字典(fault dictionary)來進行有效地區分程序，接著利用診斷結果來描繪出錯誤行為位元圖(fault bit-maps)，提供更進階的錯誤診斷資訊以方便、快速地改善良率與產品可靠性。我們也提出了一個內建自我診斷電路(Built-In Self Diagnosis; BISD)，用來收集有用的測試資料並供給外部之錯誤診斷系統進行分析，此內建自我診斷電路更採用了獨特的工程測試模式控制功能，用以縮短測試所需花費的時間，也提供平行輸出測試資料來降低資料輸出時間。同時，此內建自我診斷電路更能提供內部平行測試的能力，大幅縮短了測試時所需花費的時間與成本。最後，我們實現了一套低成本可配置之診斷系統，並實際使用工業界快閃記憶體產品來驗證我們提出之低成本可配置之診斷系統，此系統有效的利用我們所提出之測試演算法(March-like Test Algorithm)來進行測試與診斷。
另一方面，我們也針對半導體記憶元件開發出一套分析與精簡測試流程，以達縮減量產測試時間之效果。我們提出了三個測試時間縮減的技術，並實現一套測試時間縮減工具來辨識重複之測試項目、提供測試項目之關聯性與建議適當之測試流程。實驗結果顯示，此測試時間縮減工具有效的降低工業界量產記憶體測試時間，並證實我們所開發之測試時間縮減工具更優於原先經由傳統統計方式縮減之成效。

With the increase in size and capacity of flash memory, long test times on complicated automatic test equipment (ATE) are now commonly seen. The test-consuming diagnosis process for ATEs results in high test cost and slow time-to-volume; thus, efficient diagnosis of flash memory has recently become a critical issue. Based on our previous work, which developed a set of disturb fault models using a systematic approach and improved March-like algorithms for both bit-oriented and word-oriented flash memory, in this work we propose cost-effective diagnostics for flash memory. The diagnosis methodology efficiently distinguishes the fault types of faulty cell from the fail bit-maps by comparing the fault signature with the fault dictionary and the fault bit-maps provide detailed diagnosis information for yield and reliability improvement. We also propose a built-in self-diagnosis (BISD) scheme that collects useful test information for off-chip diagnosis analysis and contains a unique test mode control that reduces test time and diagnostic data shift-out cycles by using a parallel shift-out mechanism. Additionally, test time is also greatly reduced by accessing the engineering test mode to do parallel programming and parallel erasing. Finally, we
show a configurable diagnostics system for low-cost test and diagnosis environment. Experiments were done using industrial flash products to justify the effectiveness of our low-cost configurable diagnostics system and the efficiency using March-like test algorithm in the test flow.

Furthermore, a systematic approach to minimize themass production test time by analyzing and rearranging the test items in the test flow is also presented in this work. We propose three test time reduction (TTR) techniques and implement an automatic TTR tool based on these techniques to identify redundant test items, suggest proper tests, and provide correlation between the test items. Experimental results show the TTR tool effectively reduces the test time of industrial memory mass production test flow; the results are on top of the original test flow that has been compacted
by conventional way based on statistics.

Introduction 1
1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 StateofTheArt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 FlashMemoryTestingFramework . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 The Proposed Approach and Contribution . . . . . . . . . . . . . . . . . . . . . . 10
5 ThesisOrganization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Background 13
1 FlashMemoryOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 OurPreviousWork—FlashMemoryTesting . . . . . . . . . . . . . . . . . . . . . 14
2.1 FunctionalFaultModels . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 TestAlgorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 FaultSimulationandAutomaticTestGeneration . . . . . . . . . . . . . . 23
3 TestTimeReduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Low Cost Fault Diagnostics for Flash Memories 29
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2 Cost-Effective Diagnosis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3 A Low Cost Configurable Diagnosis System . . . . . . . . . . . . . . . . . . . . . 34
Built-In Self-Diagnosis Design 36
1 BISDArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2 HighVoltageTestControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3 InternalParallelTest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4 Parallel Export of Diagnostic Data . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Flash Diagnostics Experimental Results 44
1 For2MbFlashMemoryChips . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2 For 256Mb Flash Memory Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Systematic Test Time Reduction Methodology 49
1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2 TestTimeReductionApproaches . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.1 Removing Redundant Test Items . . . . . . . . . . . . . . . . . . . . . . . 51
2.2 MergingTestPatterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.3 DevelopingNewTestPatterns . . . . . . . . . . . . . . . . . . . . . . . . 54
3 ApplicationtoFlashMemory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4 Proposed TTR Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Test Time Reduction Experimental Results 64
1 Industrial DRAM Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2 Industrial Flash Memory Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Conclusions 68
Future Work 70
1 Defect-Based Diagnosis Methodology . . . . . . . . . . . . . . . . . . . . . . . . 70
2 EfficientFailureAnalysisStrategy . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3 YieldEnhancement byCost-EffectiveRepairScheme . . . . . . . . . . . . . . . . 71
4 Reliability Verification and Enhancement . . . . . . . . . . . . . . . . . . . . . . 72
Bibliography 73

                                

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