矽和鍺元素本身之間存在晶格常數的不匹配，可藉其自然晶格常數的差異來產生應力。若磊晶厚度在臨界厚度之下，可產生足夠應力以提升載子遷移率，故磊晶多層堆疊矽/鍺薄膜在SOI FinFET的通道上。由不同磊晶厚度之矽和鍺薄膜來產生不同的鍺含量在通道內之比例，形成具有矽鍺超晶格通道結構之鰭式電晶體元件，以達成更高的載子遷移率。本研究引進低溫微波作為離子佈植後之退火可達到好的活化摻雜退火，其製程溫度可以控制在400 ~500 oC左右。相較於傳統高溫快速熱退火，可抑制源極與汲極在摻雜活化後雜質擴散嚴重而造成短通道效應，也能抑制高介電係數介電層因高溫使等效氧化層厚度的增加。
第一部分，首先使用磊晶多層堆疊矽/鍺薄膜在SOI基板上，成功完成具有多層矽/鍺超晶格的鰭式電晶體元件。實驗結果發現，經過磊晶超晶格通道(2 Periods Si/Ge)之後的FinFET相較單晶矽的通道結構有更佳的電特性，電性上如較高的汲極電流、轉導值、Ion/Ioff ratio以及載子遷移率方面等，與較小的次臨界擺幅。推測原因是具有應力的鍺可提供較高載子遷移率，及有一層Si cap在通道上會使得鍺較不易擴散至介面。此外，發現以矽/鍺超晶格通道(2 Periods Si/Ge=25Å/25Å)在Ion/Ioff ratio、汲極電流、Gm、mobility的效果最好，整體皆明顯較優於其餘通道之元件，在矽鍺通道上成長一矽覆蓋層能提升應力、減少鍺向上擴散的現象。
第二部分，延續前一章節製作出矽/鍺超晶格通道(2 Periods Si/Ge=25Å/25Å)的電晶體元件。為了提升介面的電特性，使用低溫微波退火、高溫快速熱退火之不同活化摻雜方式，除了能達到活化效果外，期望低溫微波退火在閘極漏電流密度和介面特性獲得更進一步改善。實驗結果發現，使用低溫微波退火之元件的Tinv可達到1.6nm及閘極漏電流減少。再者，元件之關閉電流減低，是因為抑制了源極與汲極在摻雜活化後導致雜質擴散及漏電流。然而，元件之驅動電流在低溫微波退火相較於高溫快速熱退火會稍微較低。

A lattice mismatch exists between silicon and germanium material ,which induces a strain in Si/Ge channel FinFET. If a Ge epitaxy layer is under its critical thickness, a strain would be generated to promote carrier mobility. Epitaxy Si/Ge super-lattice is applied for SOI FinFET device in this thesis. Effects of Ge ratios in Si/Ge channel and are studied with different Si/Ge layer thicknesses as during epitaxy process.Higher carrier mobility in FinFET may be achieved by Si/Ge super lattice channel. A low-temperature microwave annealing is applied to achieve good activation after ion implantation, and its temperature can be around 400 ~500 oC . Compared to rapid thermal annealing , short channel effect induced by dopant diffusion can be suppressed by a microwave annealing for thermal activation . Also, the increases in equivalent oxide thickness of high-k dielectric layer after high temperature process may be minimized.
In the first part, Si/Ge multi-layers are epitaxially grown layer-by-layer on SOI substrate. FinFET with Si/Ge super lattice channel is successfully fabricated in this thesis. Experimental results show that electrical characteristics of device with Si/Ge super lattice are better as compared to those of control sample, such as higher drain current, transconductance , Ion/Ioff ratio and carrier mobility .The improvement can be attributed to the strained Si/Ge super lattice and suppressed Ge diffusion by Si cap. Moreover , electrical characteristics of device with Si/Ge super lattice channel formed by 2 Periods Si/Ge=25Å/25Å are the best among all samples, such as drain current, Ion/Ioff ratio, transconductance, mobility. Thus, Si cap on Si/Ge super lattice channel can achieve higher strain effect and lower Ge up-diffusion.
In the second part, FinFET with Si/Ge super lattice is used according to the results of the 1st part. In order to continuously promote electrical characteristics of FinFET, low-temperature microwave and rapid-thermal annealing treatments for dopant activation are investigated. Experimental results show that Tinv of 1.6nm and low gate leakage are achieved by a microwave annealing. Also, the off current of FinFET is reduced because the leakage current is suppressed by reducing dopants diffusion during activation process .However, the drain on current of device with a microwave annealing is smaller as compared to that with rapid thermal annealing.

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