隨著製程的進步，在超大型積體電路設計中，漏電流(leakage current)的消耗慢慢主導整個功率的消耗。MTCMOS的設計方法可以有效的減少漏電流的發生，以群組為基礎的(cluster-based)MTCMOS設計將整個電路分成很多群組，每一個群組是將互相不會同時放電的元件擺在一起，並且連接相同的睡眠電晶體(sleep transistor)。
[3]是一個以群組為基礎的MTCMOS研究，同時考慮了電路的拓撲(topology)和功能性(functionality)，發現更能夠減少所需要的sleep transistor數目。但是這一類以群組為基礎的MTCMOS設計，並沒有考慮到元件配置(cell placement)的問題，可能會造成總繞線(total wirelength)長度很大的問題，導致更多功率的消耗等問題的產生。因此我們參考了[3]的方法，針對以群組為基礎的MTCMOS設計，提出了兩種標準元件(standard-cell)配置(placement)的演算法，同時去減少總繞線長度的增加，和減少睡眠電晶體所需要的數目。
第一種方法是以功能性為導向(functionality-directed)的配置演算法，第二種方法是直接配置(direct-placement)加上元件搬動(cell-moving)的配置演算法。根據實驗的結果第一種方法可以減少9.18%的晶片面積但是會增加5.16%的總繞線長度，第二種方法可以減少14.38%的晶片面積但是會增加32.43%的總繞線長度。

Reducing power dissipation is one of the most important issues in VLSI design today. Multi-Threshold CMOS (MTCMOS) is a circuit style that can effectively reduce leakage power consumption. The cluster-based MTCMOS design is proposed to reduce the virtual ground overhead. The sleep
transistor size can be reduce by clustering mutual exclusive discharge cells together to minimize the simultaneous switching current per cluster and to share one sleep transistor per cluster. From [3], the sleep transistor size can be further reduced by considering topology and functionality simultaneously. However, this cluster-based MTCMOS design do not consider the placement
issue. Therefore, we propose two standard cell placement algorithms for MTCMOS design to minimize wirelength overhead and sleep transistor size. The first one is a functionality directed placement algorithm and the second
one is a direct placement with iterative cell-moving algorithm. The experimental results show that the chip area is reduced about 14.38% and the total wirelength increased about 32.43% compared to the direct placement by performing the functionality directed placement algorithm, and the chip
area is reduced about 9.18% and the total wirelength increased about 5.16% compared to the direct placement by performing the direct placement with iterative cell moving algorithm.

[1] Mohab Anis, Shawki Areibi, Mohamed Mahmoud, and Mohamed El-
masry, "Dynamic and Leakage Power Reduction in MTCMOS Circuits
Using an Automated E±cient Gate Clustering Technique," Proceedings
of the 39th conference on Design automation, pp. 480-485, 2002.
[2] James Kao, Siva Narendra, Anantha Chandrakasan, "Subthreshold leak-
age modeling and reduction techniques," Proceedings of ICCAD, pp. 141
- 148, 2002.
[3] Tsuang-Wei Chang, Ting-Ting Hwang, Sheng-Yu Hsu, "Functionality
Directed Clustering for Low Power. MTCMOS Design," Proceedings of
ASP-DAC, pp.862-867,2005
[4] BSIM3 Homepage. http://www-device.eecs.berkeley.edu»bsim3/arch ftp.html.
[5] Dongwoo Lee and David Blaauw, "Static Leakage Reduction through
Simultaneous Threshold Voltage and State Assignment," Proceedings
of the 40th conference on Design automation, pp. 191-194, 2003.
[6] Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-
Myung Choi, Jeong-Taek Kong, "An MTCMOS Design Methodology
and Its Application to Mobile Computing," Proceedings of ISLPED,
pp. 110 -115, 2003.
[7] Rahul M. Rao, Frank Liu, Je®rey L. Burns, and Richard B. Brown,
"A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS
Combinational Circuits," Proceedings of ICCAD, pp. 689-692, 2003.
[8] Dongwoo Lee, Harmander Deogun, David Blaauw, and Dennis Sylvester,
"Simultaneous State, Vt and Tox Assignment for Total Standby Power
Minimization," Proceedings of DATE, pp. 494-499, 2004.
[9] Yen-Te Ho, TingTing Hwang, "Low Power Design Using Dual Threshold
Voltage," Proceedings of ASP-DAC, pp. 205-208, 2004.
[10] M. Wang, X. Yang, M. Sarrafzadeh, "Dragon2000: Standard-cell Place-
ment Tool for Large Industry Circuits," Proceedings of ICCAD, pp.260-
263, 2000.
[11] S.Muth, T.Douseki, T.Matsuya, T.Aoki, S.Shigematsu, and J.Yamada,
"1-V Power Supply High-Speed Digital Circuit Technology with
Multithreshold-Voltage CMOS," IEEE Journal of Solid-State Circuits,
vol. 30, no. 8, pp. 847-853, Feb. 1995.
[12] J.Kao, A.Chandrakasan, and D.Antoniadis, "Transistor Sizing Issues
and Tool for Multi-threshold CMOS Technology," Proceedings of the
34th conference on Design automation, pp. 409-414, 1997.
[13] J.Kao, S.Narendra, and A.Chandrakasan, "MTCMOS Hierarchical Siz-
ing Based on Mutual Exclusive Discharge Patterns," Proceedings of the
35th conference on Design automation, pp. 495-500, 1998.
[14] Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj, "Pattern Independent
Maximum Current Estimation in Power and Ground Buses of CMOS
VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution,"
IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, pp. 998-1012, 1995
[15] Sablh H. Gerez, "Algorithms for VLSI Design Automation," pp. 265-
267.