本論文主要討論 3GPP (Release 4 and Release 5)文件中提出的高速下傳封包接收(HSDPA)系統及其基頻收發機處理器架構設計、電路設計之研究。

論文內容先對行動通訊系統及分碼多工存取技術做簡介，之後對整個 3GPP 寬頻分碼多工存取(WCDMA)傳輸系統及高速下傳封包接收技術做敘述介紹。在接收機設計方面，對於每一個接收機所用到的接收技術，著重在演算法的採用與最佳化電路設計，以便達到實作上能夠盡量減少在面積及功率消耗上的需求。

在無線通道估測中，我們採用了多重判斷偵測(Multiple-dwell Detection)方式來降低通道估測器的中匹配濾波器(Matched Filter)的複雜度與功率消耗。另外對於在資料傳輸中所遭遇到的載波頻率及取樣時脈誤差，我們也提出相對應且較實際的補償架構。最後在接收資料回復上，採取時域(Time Domain)上的最小均方適應性等化(LMS Adaptive Equalization)來取代傳統展頻通訊中較常用的犁耙式接收(Rake Combining)以有效的對抗多路徑效應所造成的符際間干擾(ISI)。最後利用多組相關器(Correlator)來對多重展頻碼傳輸的接收資料做解展頻動作。

整個收發機系統的模擬則是透過所建立的無線通道模組來模擬資料從發射機到接收機端之間所遭受到的通道不理想效應以及收發端載波頻率、取樣時脈的不匹配現象。而通道的多路徑衰減傳播條件則是採用3GPP 中所提供的模擬環境。

最後我們從所提出的電路架構對整個收發機設計在硬體考量上扮演較重要角色的兩個部分: 匹配濾波器、最小均方適應性等化器做初步定量的比較與評估。透過這些比較評估可較清楚了解匹配濾波器電路經演算法的改善可以達到硬體面積與功率損耗的減省以及在之後整個收發機於電路設計實作所要著重的地方。

In this thesis, WCDMA communication systems and HSDPA systems are presented. Then, we propose a baseband transceiver architecture for HSDPA communication systems and its circuit design.

In order to improve the transmission data rate in downlink WCDMA communication systems, 3GPP has proposed HSDPA communication systems in Release 4 and Release 5 documents. After system specification description, a baseband transceiver for HSDPA communication systems is proposed. In this proposed transceiver, we focus on receiver design. We use Common Pilot Channel (CPICH) to achieve channel estimation and restore High-Speed Share Control Channel (HS-SCCH) and High-Speed Physical Downlink Share Channel (HS-PDSCH) data. Receiver can mainly be divided into four parts: synchronization, equalization, de-spreading and symbol recovery. The synchronization part includes a channel estimator, a carrier frequency synchronization, and a timing synchronization. In channel estimator, the multiple-dwell detection is introduced to minimize the size and power consumption of matched filter. Besides, applicable algorithms is adopted to design the frequency synchronization loop, timing synchronization loop, and adaptive equalizer base on low cost and practical criterion but without losing performance even better. The detail architecture and algorithm of each reception technique in receiver will be presented in the thesis.

After system functional simulation based on propagation conditions of multi-path Doppler fading environment in 3GPP for HSDPA with carrier frequency and timing offset inserted, the circuit design of the proposed HSDPA transceiver will be mentioned.

Matched filter and time domain LMS equalizer are the dominant components in receiver. Via coarse comparison and evaluation of the hardware cost and computation complexity, hardware reduction from modified detection algorithm and the emphasis of hardware implementation of whole receiver can be addressed clearly. Finally, some future works and the conclusions of this thesis will be given.

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