在現今的三維度積體電路的製造產業中，除了時脈網路的設計與規劃是一件相當困難的任務之外，如何詳細的策畫針對時脈網路的測試方法也是一大挑戰。除此之外，在現今的研究已經明確指出，對於那些會對時脈訊號的偏移量感到非常敏感且無法自動適應調整的高效能表現電路設計而言，時脈訊號網路上只要出現了一些微小的瑕疵，就有很大可能會在晶片出場後引發某種在預期之外的失誤。因此，為了增加晶片製造的良率和確保其可靠度，未來在晶片製造出場前的製造測試或功能性測試的過程當中，必然需要有能力將這樣的瑕疵給檢定甚至診斷出。在這篇論文當中，我們呈獻了一種創新的測試方法，此測試方法可以幫助我們判斷時脈訊號網路上是否有任何微小的延遲錯誤。這個方法完全不需要對時脈訊號網路做出任何的改變更動，其更是有辦法透過離群值數據分析方法，偵測到將近40皮秒的微小延遲錯誤，同時判定出有哪些正反器是會被這個偵測到的延遲錯誤所影響。還有一點，由於我們所提出的測試方法其過程中所使用的測試訊號，並不會對待測目標電路造成而外的負擔，也不會因為其待測目標電路的不同而需要更換別種測試訊號。換句話說，在必要的時候這樣的測試方法是可以非常容易地藉由一內建自測試控制器而進行操作。

A clock network in a 3D-IC is not only difficult to design, but also challenging to test. For high-performance designs with a rigorous clock-skew requirement, studies have shown that small defects in a clock tree network could lead to unexpected failures in the field and thus it need to be identified during the manufacturing test or functional test in order to improve the yield and maintain the reliability. In this thesis, we present a novel test method to determine if a clock network has any small delay fault. This method does not require any change of the clock network, and it is capable of detecting a delay fault as small as 40ps through outlier analysis, while locating the FFs affected by the fault in the meantime. Furthermore, the overall test process does not involve loading of test patterns and thus can be conducted very easily by a Built-In Self-Test (BIST) controller when it needed.

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