適用於多使用者多輸出多輸入下漏訊號預編碼之基於平方根演算法改進廣義特徵值分解處理器設計與實作

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研究生：	李凌 Lee, Ling
論文名稱：	適用於多使用者多輸出多輸入下漏訊號預編碼之基於平方根演算法改進廣義特徵值分解處理器設計與實作 Design and Implementation of Modified Generalized Eigenvalue Decomposition Processor based on Square-Root Algorithm for Leakage-based Precoding in MU-MIMO Systems
指導教授：	黃元豪 Huang, Yuan Hao
口試委員:	蔡佩芸 Tsai, Pei Yun 賴以威 Lai,I Wei
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 通訊工程研究所 Communications Engineering
論文出版年：	2016
畢業學年度：	104
語文別：	英文
論文頁數：	74
中文關鍵詞：	多用戶、多輸出輸入、漏訊號預編碼、廣義特徵值分解、平方根演算法
外文關鍵詞：	Square-Root algorithm
相關次數：	點閱：2 下載：0
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查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

為了增進無線通訊的速度和可靠度，多使用者多輸出多輸入通訊系統成為相當熱門的研究主題。在此下傳通訊系統中，基地台必需使用預編碼來消除同頻干擾。下漏訊號預編碼是適用於多使用者多輸出多輸入通訊系統的一種預編碼。與其他預編碼相比，下漏訊號預編碼有較低的錯誤率以及複雜度。廣義特徵值分解是下漏訊號預編碼中必要的運算步驟也是運算複雜度最高的步驟。因此這篇論文提出一個硬體演算法來加速廣義特徵值分解的運算。與原本的廣義特徵值分解演算法相比，提出的演算法在理論的分析和實作上有較少乘法數以及較短的延遲。論文中也呈現了關於提出演算法的硬體架構。接著藉由FPGA驗證此硬體架構的面積及速度。我們也拿本研究在TSMC 90nm的合成結果與其他研究進行面積和速度上的比較。論文的最後，我們使用TSMC 40nm將本研究實現成晶片並列出晶片規格。

In order to improve the speed and reliability in current wireless communication system, multiuser MIMO (MU-MIMO) has become a popular research topic. For suppressing co-channel interference, it is necessary to design a precoding scheme for MU-MIMO downlink communication system. Leakage-based precoding scheme is a popular scheme for MU-MIMO communication system because of good performance. By adopting leakage-based precoding scheme, generalized eigenvalue decomposition (GEVD) is not only an inevitable process but also a complicated operation to calculate the precoder. Therefore, a GEVD hardware algorithm is proposed for decreasing computational time in this thesis. Compared to the conventional GEVD algorithm, the proposed algorithm has the less number of multiplications and shorter latency according to the theoretical analysis and practical implementation. The architecture of the proposed algorithm is presented in the following content. The proposed algorithm is implemented and verified by FPGA. The synthesis results in terms of FPGA and TSMC 90nm/40nm are shown. In the end of thesis, the architecture of the proposed algorithm is implemented as chip with TSMC 40nm and the specifications of the chip are presented.

Introduction 3
1 Multi-User MIMO (MU-MIMO System) .................. 3
2 Motivation ................................... 5
3 Thesis Organization .............................. 5
MU-MIMO System and Precoding Scheme 7
1 MU-MIMO System Model .......................... 7
2 MU-MIMO Precoding Scheme ........................ 8
2.1 BD-Based Precoding Scheme ..................... 9
2.2 Leakage-Based Precoding Scheme ................ 11
Generalized Eigenvalue Decomposition 13
1 Definition of GEVD .............................. 13
2 Implementation of GEVD .......................... 16
2.1 Cholesky Decomposition ....................... 17
2.2 Jacobi Method ............................ 20
2.3 Dificulties of Implementation of GEVD .......... 23
Proposed Modified GEVD based on Square-Root Algorithm ...........25
1 Square-Root Algorithm ............................ 25
1.1 Square-Root Algorithm for BLAST MIMO Detection . 25
1.2 Square Root of P Inverse ....................... 27
2 Elimination of Q Matrix ......................... 29
3 Modified Jacobi Method ........................... 30
4 Result ..................................... 33
Architecture Design 37
1 System Architecture ............................. 37
1.1 CORDIC Processor .......................... 38
1.2 Architecture of Square Root of P Inverse .... 40
1.3 Architecture of Reduced Matrix Multiplier ...... 44
1.4 Architecture of Jacobi Method .................. 44
1.5 Eigenvalue Sort ............................ 50
1.6 Timing Schedule ........................... 51
2 Fixed-point Simulation .......................... 52
3 FPGA Verification .............................. 59
4 FPGA Synthesis Result ........................... 60
5 Synthesis Result ................................ 61
6 Chip Implementation ............................. 61
6.1 Design Flow .............................. 62
6.2 Chip Layout and Specification .................. 64
6.3 Chip Simulation and Verification ............... 67
Conclusion 71
                                

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