矽製程後時脈偏斜調整架構的分析與最佳化｜國立清華大學博碩士論文庫

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研究生：	高聿謙 Kao, Yu-Chien
論文名稱：	矽製程後時脈偏斜調整架構的分析與最佳化 Analysis and Optimization of the Post-silicon Skew Tuning Architecture
指導教授：	張世杰
口試委員:	張世杰王進賢麥偉基黃世旭李毅郎
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2013
畢業學年度：	101
語文別：	英文
論文頁數：	85
中文關鍵詞：	時脈偏斜、矽製程後調整架構
相關次數：	點閱：1 下載：0
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時脈偏斜最佳化一直以來是重要的設計考量，但是現今製程電壓與溫度的變異造成最佳化的難度不斷上升。為了減低這些變異造成的影響，許多學者矽製程後調整架構來動態調整時脈數中的時脈偏斜。在時脈偏斜架構中，有兩個重要的元件：可調變延遲之緩衝器以及相位偵測器。本論文中就是針對此架構中許多重要的問題進行分析與最佳化。

Clock skew minimization is an important design consideration. However, with the advance of the technology and the smaller device scaling, Process, Voltage, and Temperature (PVT) variations make the clock skew minimization face great challenges. To mitigate the impact of PVT variations, many previous works proposed the Post Silicon Tuning (PST) architecture to dynamically balance the skew of a clock tree. In the PST architecture, there are two main components: Adjustable Delay Buffer (ADB) and Phase Detector (PD). In this thesis, we analyze the several interesting design issues of the PST architecture and optimize them such as the PD connection, system controlling, and design testing to the PST architecture.

Content
ABSTRACT    1
CONTENT    2
LIST OF FIGURES    5
CHAPTER 1    INTRODUCTION    7
1    THE POST-SILICON SKEW TUNING ARCHITECTURE    7
2    ORGANIZATION    10
2.1    The Phase Detector Connection Structure for the PST Architecture    10
2.2    An Efficient Controlling Structure for Post-silicon Skew Tuning Architecture    15
2.3    The Robust Architecture for Post-Silicon Skew Tuning    19
CHAPTER 2    THE PHASE DETECTOR CONNECTION STRUCTURE FOR THE POST-SILICON SKEW TUNING ARCHITECTURE    21
1    PRELIMINARIES AND PREVIOUS WORKS    21
2    THE INACCURACIES OF THE SKEW SYNCHRONIZATION SCHEME    23
2.1    The Sampling Inaccuracy Caused by Sampling Clock Signals    23
2.2    The Resolution Inaccuracy Caused by ADB Limitations    25
2.3    The Intrinsic Inaccuracy of Two Connecting FFs    25
2.4    The Accumulation of the Intrinsic Inaccuracy on a Serial Chain    26
2.5    Finding the Global Intrinsic Inaccuracy of a Circuit    27
3    PROBLEM FORMULATION AND THE OPTIMAL SPANNING TREE SOLUTION    29
3.1    Problem Formulation and Basic Ideas of Our Algorithm    29
3.2    Determination of an Initial PD Tree Structure    30
3.3    Determining an Initial PD Tree Structure with Both the Resolution and Estimated Sampling Inaccuracy    33
3.4    The Iterative Heuristic for Minimizing the Global Intrinsic Inaccuracy    34
4    EXPERIMENTAL RESULTS    36
5    CONCLUSIONS    38
CHAPTER 3    AN EFFICIENT CONTROLLING STRUCTURE FOR POST-SILICON SKEW TUNING ARCHITECTURE    39
1    THE REPRESENTATIVE FF AND PD TREE STRUCTURE    39
2    THE LOCALIZED CONTROL SCHEME    41
3    THE ADB FLOW CONTROL    42
4    THE DETERMINATION OF THE LOCAL-FEASIBLE ADB FLOW CONTROL    44
5    TWO ALGORITHMS FOR CONSTRUCTING PD STRUCTURES    48
6    THE SAMPLING INACCURACY    50
7    PROBLEM FORMULATION AND PROPOSED ALGORITHM    53
8    EXPERIMENTAL RESULTS    56
9    CONCLUSIONS    59
CHAPTER 4    THE ROBUST ARCHITECTURE FOR POST-SILICON SKEW TUNING    60
1    PRELIMINARIES    60
1.1    The ADB and PD Designs    60
1.2    The PST Architecture    61
1.3    Synchronizer    64
2    FAULT MODELING OF THE SYNCHRONIZERS    65
3    BASIC PST TESTING FLOW AND THE TESTING ARCHITECTURE    67
4    THE SCAN CHAIN ARCHITECTURE FOR FAULT DIAGNOSIS    70
5    THE FAULT TOLERANCE ARCHITECTURE    73
5.1    The Fault Tolerance Mechanism    73
5.2    The Rules of Selecting Redundant PDs    76
5.3    The Proposed Structure for Redundant PD Connection    78
6    EXPERIMENTAL RESULTS    80
7    CONCLUSIONS    82
REFERENCES    84

                                

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