研究生: |
林華勁 Hwa-Jin Lin |
---|---|
論文名稱: |
可處理任意形狀結構元素的灰階影像型態學運算之高速架構之研究 High Speed Architecture for Gray-level Morphological Operations with Arbitrary Shape Structuring Elements |
指導教授: |
陳永昌
Yung-Chang Chen |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2006 |
畢業學年度: | 94 |
語文別: | 英文 |
論文頁數: | 56 |
中文關鍵詞: | 型態學 、結構元素 |
相關次數: | 點閱:1 下載:0 |
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形態學運算是以對一樣圖形物件的形狀及結構進行分析,或研究不同圖形物件間之關係的一種數學工具。在現今的數位影像處理中,這項由集合論為根基所推導出的數學工具已被廣泛的應用在如影像切割、影像增強及影像壓縮等等。
這些延伸的應用,都是由最基本的兩個形態學運算所推導而出:擴張運算及侵蝕運算。然而這些由擴張運算與侵蝕運算所延伸出的應用所須的計算複雜度,也因此而直接受到這兩項基本運算的複雜度影響。故此,是否能夠設計一個高速的硬體架構來實現這兩項基本運算,將是愈來愈重要的課題。在這篇論文之中,提出了一個能夠針對灰階影像進行擴張運算及侵蝕運算,並能達到相當快的運算速度且硬體成本不致因此而增高的硬體架構。除此之外,這篇論文所提出的架構尚能對任意形狀的結構元素進行處理,也是另一項符合未來形態學運算趨勢的優點。實驗是以FPGA進行驗證,所得的數據亦顯示出這個形態學運算硬體架構在速度及適應性上的良好表現。
The main issue on morphological operations is the analysis of the shape and structure of an object, or dealing with the relationship of different objects. In the field of digital image processing, we could make use of this mathematical tool which is highly related to the set theory for shape-based image processing, such as image segmentation, image enhancement, pattern recognition, image compression, etc. The basis of these various applications is erosion and dilation. All the methodologies utilize these two basic functions. Nevertheless, these advanced morphological operations take great computing complexities based on erosion and dilation. Designing a high speed architecture to implement the function of erosion and dilation would be an important issue. In this thesis, we propose an architecture that can achieve relatively high speed and low hardware cost to deal with the gray-level erosion and dilation of arbitrary-shaped structure elements. Experiment is conducted with the use of FPGA, showing the great performance of the proposed architecture.
[1] Frank Y. Shih, Chung Ta King and Christopher C. Pu, “Pipeline architecture for recursive morphological operations”, Image Processing, pp.11-18, vol. 4, January, 1995
[2] Basilios Gatos and Stavros J. Perantonis, “Fast Implementation of morphological operations using binary image block decomposition”, International Journal of Image and Graphics, pp.1-21, vol.4, December, 2003
[3] Rafael C. Gonzalez and Richard E.Woods, “Digital Image Processing, 2nd Ed”, Prentice Hall
[4] Jorg Velten and Anton Kummert, “Implementation of a high-performance hardware architecture for binary morphological image processing operations”, IEEE Trans. On Circuits and Systems, pp. II-241-II-244, vol. 2, July, 2004
[5] Xilinx, “Spartan and Spartan-XL families field programmable array”
[6] Ulinx, “Spartan 3 embedded system kit”
[7] Jorg Velten and Anton Kummert, “High-speed FPGA implementation of multidimensional binary morphological operations”, IEEE Trans. On Circuits and Systems, pp. III-706-III-709, vol.3, May, 2003
[8] Soohwan Ong and Myung H. Sunwoo, “A new cost-effective morphological filter chip”, Signal Processing Systems SIPS 97 - Design and Implementation., 1997 IEEE Workshop, pp. 421-430, November, 1997
[9] EN. Malamas, A.G. Malamos, and T.A. Varvarigou, “Fast implementation of binary morphological operations on hardware-efficient systolic architectures,” IEEE Journal of VLSI Signal Processing, vol. 25, pp.79-93,2000.
[10] Giovanni Anelli, Alberto Broggi and Giulio Destri, “Decomposition of arbitrary shaped binary morphological structuring elements using genetic algorithms”, IEEE Trans. On Pattern Analysis and Machine Intelligence, pp. 217-224, vol. 20, no.2, February, 1998
[11] Hochong Park and Roland T. Chin, “Decomposition of arbitrarily shaped morphological structuring elements”, IEEE Trans. On Pattern Analysis and Machine Intelligence, pp. 2-15, vol. 17, January, 1995
[12] H. T. Yang and S. J. Lee, “Decomposition of morphological structuring elements with integer linear programming”, Vision, Image and Signal Processing, IEE proceedings, pp. 148-154, vol. 152, April, 2005
[13] Shao-Yi Chien, Shyh-Yih Ma and Liang-Gee Chen, “Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements”, IEEE Trans. On Circuits and Systems for Video Technology, pp. 1156-1169, vol. 15, September, 2005
[14] I. Pitas, “Fast glorithms for running ordering and max/min calculation,” IEEE Trans. on Cirsuits and Systems, pp.795-1304, vol. 36, no. 6, June, 1989.
[15] D. Coltuc and I. Pitas, “Fast computation of a class of running filters,” IEEE Trans. on Signal Processing, pp.549-553, vol. 46, no. 3, March, 1998.
[16] K.1. Diamantaras and S.Y. Kung, “A linear systolic array for real-time morphological image processing,” IEEE Journal of VLSI Signal Processing, vol. 17, pp.43-57,1997.
[17] PA. Ruetz and R.W. Brodersen, “Architectures and Design Techniques for Real-Time Image-Processing IC’s,’’ IEEE Journal of Solid-state Circuit, vol. sc-22, no. 2, pp.233-250, April, 1987.
[18] M.-H. Sheu, J.-E Wang, J.-S. Chen, A.-N. Suen,Y.-L. Jeang, and J.-Y. Lee, “A data-reuse architecture for gray-scale morphologic operations,” IEEE Trans. on Circuits and Systems- 1’1 Analog and Digital Signal Processing, vol. 39, no. 10, pp.753-756, October, 1992.