應用於有線通訊13.6Gb/s全速率全數位式時脈與資料回復電路

簡易檢索 / 詳目顯示

回結果列表

研究生：	賴津寅 Lai, Chin-Yin
論文名稱：	應用於有線通訊13.6Gb/s全速率全數位式時脈與資料回復電路 A 13.6Gb/s Full rate All Digital Clock and Data Recovery for Serial Link
指導教授：	朱大舜 Chu, Ta-Shun 彭朋瑞 Peng, Pen-Jui
口試委員:	王毓駒 Wang, Yu-Jiu 吳仁銘 Wu, Jen-Ming
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2023
畢業學年度：	111
語文別：	中文
論文頁數：	83
中文關鍵詞：	時脈與資料回復電路、全數位式時脈與資料回復電路
外文關鍵詞：	CDR, All Digital CDR
相關次數：	點閱：33 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

本論文實現應用於13.6Gb/s全速率全數位式時脈與資料回復電路。全數位式時脈與資料回復電路相較於傳統類比式時脈與資料回復電路透過減少類比電路的使用有著較好的抗雜訊能力及抗製程變異能力且容易隨著製程演進而設計。
本論文利用電流邏輯完成高速二位元相位偵測器，而積分路徑則是使用一對十六解多工器與多數決電路並送入累加器去完成頻率累積動作，並利用掃描鍊去達到輔助鎖定之功能。而為了有夠大的調整範圍數位控制振盪器則是採用環型振盪器。
論文首先介紹高速串列訊號傳輸的概念，並接著介紹時脈上會應用的概念以及時脈與資料回復電路的架構，再利用數學分析時脈與資料回復電路的指標，並透過大量模擬去對各項指標進行探討，接著則是詳細的去比較所使用的每個子電路特性與操作，最後附上電路的結果與佈局，本論文使用TSMC 65nm CMOS製程。整體系統功耗為43.62mW。

This paper mainly implements the all-digital clock and data recovery circuit applied to the full rate of 13.6GHz. Compared with the traditional analog clock and data recovery circuit, the all-digital clock and data recovery circuit has better immunity to noise and better adaption to process variation by reducing the use of analog circuits. Furthermore, all-digital clock and data recovery is easier to design as the process evolution.
In this thesis, a high-speed Bang-Bang phase detector is implemented by using current mode logic. The integral path is completed by using a one to sixteen demultiplexers and a majority vote circuit and sending them to the accumulator to complete the frequency accumulation, and uses the scan chain to achieve the auxiliary locking function. In order to have a large enough tuning range, the digital control oscillator use ring oscillator.
The paper first introduces the concept of high-speed serial signal transmission, and then introduces the concepts that will be applied to the clock and the structure of the clock and data recovery circuit, and then uses mathematics method to analyze the clock and data recovery circuit in this thesis, and through a large number of simulations to find the trend of each index is carried out, followed by a detailed comparison of the characteristics and operation of each sub-circuit used, and the results and layout of the circuit are attached in the last. This paper uses TSMC 65nm CMOS process. The overall system power consumption is 43.62mW。

摘要    i
Abstract    ii
誌謝    iii
目錄    iv
圖目錄    vii
表目錄    xii
第一章 緒論    1
1 研究背景與動機    1
2 論文架構    2
第二章 時脈資料回復電路簡介    3
1 隨機二進制資料特性    3
2 偽隨機碼(Pseudo-Random Binary Sequence)    4
3 時脈抖動介紹    6
3.1 資料相依性抖動(Data Dependent Jitter)    6
3.2 責任週期失真抖動(Duty-Cycle-Distortion Jitter)    9
3.3 週期性抖動(Periodic Jitter)    9
3.4 隨機抖動(Random Jitter)[1]    10
4 誤碼率(Bit error rate)    10
5 眼圖與浴缸曲線介紹[2]    11
6 時脈與資料回復電路原理與架構    12
6.1 時脈與資料回復電路概念    12
6.2 鎖相迴路為基底之時脈回復電路    12
6.3 相位插值器為基底之時脈回復電路    15
第三章 時脈與資料回復電路之系統分析    17
1 操作速率    17
2 類比式CDR與數位式CDR比較    18
3 時脈與資料回復電路指標    19
3.1 抖動產生(Jitter Generation)    19
3.2 抖動轉移(Jitter transfer)    21
3.3 抖動容忍Jitter tolerance    24
4 系統分析    26
4.1 抖動轉移系統分析    26
4.2 參數模擬對抖動轉移的影響    27
4.3 參數模擬對抖動容忍影響    29
4.4 延遲對時脈抖動影響    31
第四章 全數位式時脈與資料回復電路實現    34
1 Verilog-A模型建立    34
1.1 Alexander PD 二位元相位偵測器模型    34
1.2 SR鎖存器模型    35
1.3 一對二解多工器    36
1.4 多數決電路    36
1.5 數位迴路濾波器_積分路徑模型    37
1.6 數位控制振盪器行為模型    38
1.7 除頻器模型    39
2 全數位時脈與資料回復電路設計    39
2.1 相位偵測器    39
2.2 D型正反器設計    47
2.3 相位偵測器模擬結果    48
3 SR鎖存器    49
4 一對十六解多工器    50
5 多數決電路    51
6 數位迴路濾波器_積分路徑    52
7 數位控制振盪器    54
7.1 LC振盪器    55
7.2 環形振盪器    59
7.3 LC數位控制振盪器之取捨    61
7.4 數位控制振盪器設計與模擬結果    62
8 除頻器    65
第五章 佈局佈線與模擬結果    67
1 二元相位偵測器    67
1.1 電流邏輯正反器    67
1.2 Alexander 相位偵測器    68
2 SR鎖存器    69
3 一對十六解多工器    69
4 多數決電路    71
5 數位迴路濾波器_積分路徑    72
6 數位控制振盪器    73
7 除頻器    74
8 時脈抖動與抖動轉移    75
9 抖動容忍    77
第六章 結論    81
1 結論    81
參考資料    82

                                

[1] K. Kundert, "Modeling jitter in PLL-based frequency synthesizers," www. designers-guide. org, 2006.
[2] K. Kundert, "Verification of Bit-Error Rate in Bang-Bang Clock and Data Recovery Circuits," The Designer's Guide Community, pp. 1-22, 2010.
[3] B. Razavi, Design of integrated circuits for optical communications. John Wiley & Sons, 2012.
[4] J. Savoj and B. Razavi, "A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector," IEEE Journal of Solid-State Circuits, vol. 36, no. 5, pp. 761-768, 2001.
[5] P. K. Hanumolu, M. G. Kim, G.-Y. Wei, and U.-k. Moon, "A 1.6 Gbps digital clock and data recovery circuit," in IEEE Custom Integrated Circuits Conference 2006, 2006: IEEE, pp. 603-606.
[6] N. Dodel and H. Klar, "10Gb/s Bang-Bang Clock and Data Recovery (CDR) for optical transmission systems," Advances in Radio Science, vol. 3, pp. 293-297, 2005.
[7] J. Lee, K. S. Kundert, and B. Razavi, "Analysis and modeling of bang-bang clock and data recovery circuits," IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1571-1580, 2004.
[8] A. Amirkhany, "Basics of clock and data recovery circuits: Exploring high-speed serial links," IEEE Solid-State Circuits Magazine, vol. 12, no. 1, pp. 25-38, 2020.
[9] X. Ge, Y. Chen, X. Zhao, P.-I. Mak, and R. P. Martins, "Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 10, pp. 2223-2236, 2019.
[10] M.-J. Park and J. Kim, "Pseudo-linear analysis of bang-bang controlled timing circuits," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 6, pp. 1381-1394, 2012.
[11] C. He and T. Kwasniewski, "Bang-Bang CDR's acquisition, locking, and jitter tolerance," in 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), 2012: IEEE, pp. 1-4.
[12] J. Kim, B. S. Leibowitz, J. Ren, and C. J. Madden, "Simulation and analysis of random decision errors in clocked comparators," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 8, pp. 1844-1857, 2009.
[13] A. G. Strollo, D. De Caro, E. Napoli, and N. Petra, "A novel high-speed sense-amplifier-based flip-flop," IEEE transactions on very large scale integration (VLSI) systems, vol. 13, no. 11, pp. 1266-1274, 2005.
[14] M. Talegaonkar, R. Inti, and P. K. Hanumolu, "Digital clock and data recovery circuit design: Challenges and tradeoffs," in 2011 IEEE Custom Integrated Circuits Conference (CICC), 2011: IEEE, pp. 1-8.
[15] B. Nikolic, V. G. Oklobdzija, V. Stojanovic, W. Jia, J. K.-S. Chiu, and M. M.-T. Leung, "Improved sense-amplifier-based flip-flop: Design and measurements," IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 876-884, 2000.
[16] I.-F. Chen, R.-J. Yang, and S.-I. Liu, "Loop latency reduction technique for all-digital clock and data recovery circuits," in 2009 IEEE Asian Solid-State Circuits Conference, 2009: IEEE, pp. 309-312.
[17] J. Choudhary, P. Balasubramanian, D. M. Varghese, D. P. Singh, and D. Maskell, "Generalized majority voter design method for N-modular redundant systems used in mission-and safety-critical applications," Computers, vol. 8, no. 1, p. 10, 2019.
[18] A. Tavakol, "Digitally Controlled Oscillator for WiMAX in 40 nm," 2012.
[19] W.-r. Wang, "具混亂時序注入機制之全數位高除數次諧波注入鎖定式鎖相迴路," National Central University, 2015.
[20] 楊于昇, "0.5 V 低功率全數位鎖相迴路設計," 2011.

簡易檢索 / 詳目顯示

相關論文