摘 要

我們設計及製作一個操作在5.7-GHz的疊接主動電感耦合式低雜訊放大器，使用台積電CMOS0.18um製程。此篇論文設計了ㄧ個能同時擁有縮小晶片面積和維持良好電路性能的新方法，就是將主動電感耦合於低雜訊放大器的源極產生抑制雜訊的功用。我們選擇在射頻電路LNA端使用主動電感，證明它能有效抑制雜訊的新重要角色。其它論文的LNA也許在某些性能上會有明顯的優點，但卻也消耗大量的螺旋電感面積，這對節省晶片面積成本沒有太大助益，因此我們設計出一套標準的主動電感應用方式，它可以有效的取代傳統螺旋電感，晶片縮小的同時，可以在相同功率消耗之下扮演抑制雜訊以及提供足夠單級增益的角色，而所有的S參數也表現優良。電感此低雜訊放大器(LNA)在5.7GHz的增益量測值為17dB以及其雜訊指數只有2.8dB。功率消耗只有19mW。晶片量測值能驗證模擬實驗的結果。
此顆5.7-GHz主動電感耦合式低雜訊放大器已下線製造出並實際量測。主動電感在先進CMOS製程下能扮演改善雜訊、維持高增益、節省晶片面積的同時也不至於增加低雜訊放大器的功率消耗。在未來更期望有更小晶片面積下，此主動電感耦合低雜訊放大器設計可以說是在射頻晶片上使用廣大面積螺旋電感的另一個非常好的選擇。

Abstract

A cascode LNA coupled with the active inductor to be a degenerated inductor for input-matching, operated at 5.7-GHz, was realized in TSMC CMOS 0.18-um process. It mentions a new method to maintain good performance and cope with the relatively small size in the same time. The LNA achieves a measured power gain of 17 dB and a noise figure of 2.8 dB at 5.7-GHz. The power consumption is only 19mW. The measured data agree with the simulation results well.
A 5.7-GHz LNA coupled with the active inductor with input-matching network has been designed, fabricated, and tested. The active inductor in newly-proposed topology plays an important role in improving noise figure, achieving high gain and optimizing power consumption of the LNA. Furthermore, smaller chip size can be obtained in the future. This work demonstrated that an active inductor implemented with a reasonable physical size seems a good alternative for its passive equivalent.

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