研究生: |
黃文政 Huang, Wen-Cheng |
---|---|
論文名稱: |
使用共同緩衝暫存器建構雙層平行雙端佇列 A Two-Level Construction of Parallel Double-Ended Queues with a Shared Buffer |
指導教授: |
張正尚
Chang, Cheng-Shang |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 通訊工程研究所 Communications Engineering |
論文出版年: | 2009 |
畢業學年度: | 97 |
語文別: | 英文 |
論文頁數: | 50 |
中文關鍵詞: | 快取 、雙端佇列 、光緩衝暫存器 、光交換機和光纖延遲線 |
外文關鍵詞: | Caches, Double-Ended Queue, optical buffer, switched delay lines |
相關次數: | 點閱:1 下載:0 |
分享至: |
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
最近的研究中,許多是有關利用光交換機和光纖延遲線實現光封包交換機的緩衝儲存器,在這篇論文中,我們利用概念上為兩層快取的平行佇列使用共同緩衝暫存器,此架構的提出者將此架構用來實現先進先出佇列,以及後進先出佇列。我們證明可以利用此架構實現另外一種緩衝暫存器,雙端佇列。雙端佇列的概念被廣泛的應用在平行電腦當中的work-stealing。而這篇論文的重要定理是定理6以及輔助定理7,和輔助定理8。
這個架構的概念是兩層的快取,第一層是由雙埠隨機要求光佇列組成,操作的時間單位是時槽,當作一個快速的儲存元件。第二層是由比率放大平行雙端佇列組成,操作的時間單位是一個時框,當作一個慢速的儲存元件。經由適當的決定轉儲門檻值以及取回門檻值,可以證明這個架構不只可以實現平行先進先出佇列,平行後進先出佇列,也可以實現平行雙端佇列。這個架構的另一個優點就是有容錯能力,透過在每一層加入額外的光學記憶體單元,這個架構仍然可以正常運作即使某些記憶體單元不能正常運作。而允許光學記憶體單元不能正常運作的個數與額外加入的光學記憶體單元個數有關。
[1] Po-Kai Huang, C. -S. Chang, Jay Cheng, and Duan-Shin Lee, Recursive
Constructions of Parallel FIFO and LIFO Queues with Switched Delay
Lines
[2] M. J. Karol, \Shared-memory optical packet (ATM) switch," in Pro-
ceedings SPIE vol. 2024: Multigigabit Fiber Communication Systems
(1993), October 1993, pp. 212{222.
[3] I. Chlamtac, A. Fumagalli, L. G. Kazovsky, P. Melman, W. H. Nelson,
P. Poggiolini, M. Cerisola, A. N. M. M. Choudhury, T. K. Fong, R. T.
Hofmeister, C.-L. Lu, A. Mekkittikul, D. J. M. Sabido IX, C.-J. Suh,
and E. W. M. Wong, \Cord: contention resolution by delay lines," IEEE
Journal on Selected Areas in Communications, vol. 14, pp. 1014{1029,
June 1996.
[4] I. Chlamtac, A. Fumagalli, and C.-J. Suh, \Multibu®er delay line archi-
tectures for e±cient contention resolution in optical switching nodes,"
IEEE Transactions on Communications, vol. 48, pp. 2089{2098, Decem-
ber 2000.
[5] J. T. Tsai, \COD: architectures for high speed time-based multiplexers
and bu®ered packet switches," Ph.D. Dissertation, University of Cali-fornia, San Diego, CA, USA, 1995.
[6] R. L. Cruz and J.-T. Tsai, \COD: alternative architectures for high
speed packet switching," IEEE/ACM Transactions on Networking,
vol. 4, pp. 11{21, February 1996.
[7] D. K. Hunter, D. Cotter, R. B. Ahmad, D. Cornwell, T. H. Gilfedder,
P. J. Legg, and I. Andonovic, \2 £ 2 bu®ered switch fabrics for tra±c
routing, merging and shaping in photonic cell networks," IEEE Journal
of Lightwave Technology, vol. 15, pp. 86{101, January 1997.
[8] C.-S. Chang, D.-S. Lee, and C.-K. Tu, \Recursive construction of FIFO
optical multiplexers with switched delay lines," IEEE Transactions on
Information Theory, vol. 50, pp. 3221{3233, December 2004.
[9] C.-S. Chang, D.-S. Lee, and C.-K. Tu, \Using switched delay lines for ex-
act emulation of FIFO multiplexers with variable length bursts," IEEE
Journal on Selected Areas in Communications, vol. 24, pp. 108{117,
April 2006.
[10] C.-C. Chou, C.-S. Chang, D.-S. Lee and J. Cheng, \A necessary and suf-
‾cient condition for the construction of 2-to-1 optical FIFO multiplexers
by a single crossbar switch and ‾ber delay lines," IEEE Transactions on
Information Theory, vol. 52, pp. 4519{4531, October 2006.
[11] C.-S. Chang, Y.-T. Chen, and D.-S. Lee, \Constructions of optical FIFO
queues," IEEE Transactions on Information Theory, vol. 52, pp. 2838{
2843, June 2006.
[12] A. D. Sarwate and V. Anantharam, \Exact emulation of a priority queue
with a switch and delay lines," to appear in Queueing Systems: Theory
and Applications, vol. 53, pp. 115{125, July 2006.
[13] H.-C. Chiu, C.-S. Chang, J. Cheng, and D.-S. Lee, \A simple proof
for the constructions of optical priority queues," submitted to Queueing
Systems: Theory and Applications, vol. 56, pp. 73-77, June 2007.
[14] C.-S. Chang, Y.-T. Chen, J. Cheng, and D.-S. Lee, \Multistage con-
structions of linear compressors, non-overtaking delay lines, and °exible
delay lines," in Proceedings of IEEE 25th Annual Conference on Com-
puter Communications (INFOCOM'06), Barcelona, Spain, April 23{29,
2006.
[15] J. L. Hennessy, D. A. Patterson, Computer Organization and Design,
San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 1997.
[16] H. R. Gail, G. Grover, R. Guerin, S. Hantler, Z. Rosberg , and M.
Sidi, \Bu®er size requirements under longest queue ‾rst," Performance
Evaluation, vol. 18, pp. 133{140, September 1993.
[17] S. Iyer, R. R. Kompella, and N. McKeown, \Designing packet bu®ers for
router linecards," Stanford University HPNG Technical Report - TR02-
HPNG-031001, Stanford, CA, Mar. 2002. also submitted to IEEE/ACM
Transactions on Networking.
[18] Pezzi, G.P.; Cera, M.C.; Mathias, E.; Maillard, N., \On-line Scheduling
of MPI-2 Programs with Hierarchical Work Stealing ,"Oct. 2007.
[19] Rober D. Blumofe, Charles E. Leiserson, \Scheduling Multithreaded
Computations by Work Stealing,"Nov. 1994.
[20] David Chase, Yossi Lev \Dynamic Circular Work Stealing Deque,"July
2005.
[21] Nimar S. Arora, Rober D. Blumofe, C. Greg Plaxton \Thread Schedul-
ing for Multiprogrammed Multiprocessors,"June 1998.