本論文使用濕式蝕刻法搭配奈米銀粒子催化反應(Silver-Nanoparticles-Catalyzed Chemical Reaction Wet-Etching)，於一般商品化之4吋單面拋光(100)面之矽晶圓背部，製作具有規律性且相同深度約4微米(μm)深度之表面大尺度奈米垂直線狀結構(Surface Large-Scale Nanowires)；本實驗室業已證實奈米垂直線狀結構具有強化基板之應力分散效果，能大幅增加晶圓的力學強度。惟其奈米垂直線狀結構應用於半導體產業之晶圓時，多道光罩之高階製程中的各項微粒會機率性地卡入結構間約100奈米(nm)的空隙(void)，造成後續製程的機台污染以及電性不穩的疑慮。故本研究致力於在保有奈米垂直線狀結構間之空隙以分散應力的前提下，沉積不影響矽晶圓本身電性並能兼容於半導體製程之保護層於奈米結構上，最終達成矽晶圓在力學方面之最大破裂強度的3倍強化，並降低在半導體製程中的微粒附著機率、達到屏蔽奈米垂直線狀結構的效果。

In this study we successfully demonstrate the silver-nanoparticles-catalyzed chemical reaction wet-etching for commercialize, single-side polished, orientation with (100) face, and 4-inch with diameter silicon wafers with regular and around 4 μm uniform depth surface large-scale patterned nanowires. And we already prove that there is the enhancement for the effect of stress distribution in the nanowires region, which means the structure of nanowires is able to enhance the strength for the silicon wafers. However, when we apply the nanowire structure into the silicon wafer for the semiconductor industry, there are chances that several kinds of particles generated from many procedures of semiconductor processes may be stuck in the voids between each nanowire, then resulting in the doubt for contaminations of instruments and instability of electrical performances. In this research, we try to deposit the protection layer which does not affect the electrical properties of silicon wafers and being compatible with the semiconductor processes upon the surface nanowires while the voids between each nanowire still exist to achieve the stress enhancement of the silicon wafers. Furthermore, the protection layer would be able to reduce the possibility for particles being stuck into the voids, achieving the effect of covered nanotexturing for applying to semiconductor industry.

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