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研究生: 李振東
Chen-Tung Lee
論文名稱: 應用於 2.4 GHz 工業/科學/醫療頻段之自動增益射頻前端
An Automatic-Gain-Control RF Front-End for 2.4-GHz ISM Band Applications
指導教授: 柏振球
Jenn-Chyou Bor
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 109
中文關鍵詞: 射頻前端自動增益控制低雜訊放大器增益控制
外文關鍵詞: RF front-end, AGC, LNA, gain control
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  • 本篇論文的主要目的在於設計一個應用在2.4 GHz工業/科學/醫療頻段頻帶可變增益的低雜訊放大器(VG-LNA)並且將它整合入射頻前端電路之中。藉由設定可變增益之低雜訊放大器的增益使其與輸入訊號功率成反比,減小混波器輸入端的振幅,進而減輕混波器對線性度的需求,也因此使得射頻前端電路的線性度得到提升。
    此外,一個包含時脈產生電路、允許自動增益控制電路(AGC enable)和數位控制電路的自動增益控制迴路被應用與整合進此射頻前端電路,用來適當的設定可變增益之低雜訊放大器的增益大小。此電路使用混頻器所輸出的中頻訊號作為時脈產生器的觸發源,因此,不需要任何額外的時脈訊號。 另外,當射頻輸入訊號足夠微弱時,時脈產生器不產生時脈訊號。此時,自動增益控制迴路是被關閉的。因此,自動增益回授控制迴路並不會影響射頻前端電路的雜訊表現。
    本論文內所有電路皆使用臺灣積體電路製造股份有限公司 0.18_μm mixed-mode 互補式金屬氧化物半導體製程實現,此具有自動增益控制的射頻前端電路其晶片面積為1.184 × 1.218 mm2。 根據模擬的結果,增益控制範圍可從7.3至36 dB 其步進增益為4.1dB。 在最大增益設定下射頻前端電路的NF從1kHz積分至10 MHz為4.6 dB,而在最小增益設定下射頻前端電路的P1dB 可達到-7.9 dBm。 自動增益控制迴路的穩定所需的時間少於19.7 μs。 在1.8伏特的電壓下,整個晶片包含輸出緩衝電路的電流為18mA, 其功率消耗為32 mW。


    In this thesis, a variable gain low noise amplifier (VG-LNA) is designed and integrated into the RF front-end for 2.4-GHz ISM band applications. By setting the VG-LNA gain inverse proportional to the input power level, the maximum input swing of the mixer is reduced so that the RF front-end linearity is improved.
    To appropriately set the VG-LNA gain, an automatic gain control (AGC) loop is added as well. It consists of a clock generator, AGC enable circuit, and digital control logic circuit. By using the IF signal as the trigger source of the clock generator, there is no need of any external clock source. Moreover, when the input RF signal is small enough, there is no clock generated from the clock generator so that the AGC loop is disabled. Therefore, the noise performance of the RF front-end is not affected by the AGC loop.
    All designed circuits are realized in TSMC 0.18_μm mixed-mode CMOS technology and the chip area of the RF front-end with AGC is 1.184 × 1.218 mm2. According to the simulation results, the total gain range is around 7.3~36 dB with 4.1 dB step. The noise figure for the maximum gain setting is 4.6 dB. The P1dB for the minimum gain setting is -7.9 dBm. The setting time of the AGC loop is less than 19.7 μs. The total power consumption including output buffer is 32 mW under 1.8 V power supply.

    Chapter 1 Introduction..…………………………………………….…1 1.1 Motivation…………………………………………………………….……1 1.2 System Overview………………………………………………….……….3 1.2.1 Wireless system standards using 2.4GHz ISM Band………….……...3 1.2.2 Receiver Architectures……………………………………….……….4 1.3 Thesis Organizations……………………………………………………....8 Chapter 2 Variable Gain Low Noise Amplifier Design…………….9 2.1 Introduction………………………………………………………………..9 2.2 Topology of Proposed LNA……………………………………………….9 2.2.1 Common-Source with Degenerative Inductor………………………..9 2.2.2 Gain Control Techniques……………………………………….…....11 2.2.3 Proposed Variable Gain LNA Circuit…………………………….….16 2.2.4 Gain Control Mechanism Analysis……………………………….....18 2.3 Noise Optimization………………………………………………………..24 2.3.1 MOS Noise Model……………………………………………………24 2.3.2 Theoretic Noise Analysis and Simulation…………………………….26 2.4 Simulation Results…………………………………………………………30 2.5 Summary…………………………………………………………………..35 Chapter 3 Down Conversion Mixer and RF Front-End …………36 3.1 Introduction……………………………………………………….…….…36 3.2 Active Down Conversion Mixer……………………………………..……36 3.2.1 Double-Balanced Gilbert-Cell Mixer……………………………..….36 3.2.2 Current Reused Technique……………………………………………40 3.2.3 Proposed Down Conversion Mixer…………………………………..41 3.3 Variable Gain RF Front-End ……………………………………………...45 3.3.1 RF Front-End Specifications…………………………………………45 3.3.2 Proposed Variable Gain RF Front-End………………………………50 3.4 Simulation Results…………………………………………………………53 3.4.1 Down Conversion Mixer……………………………………………..53 3.4.2 RF Front-End…………………………………………………………56 3.5 Summary…………………………………………………………………..62 Chapter 4 Automatic Gain Control ………………………………63 4.1 Introduction……………………………………………………………….63 4.2 Automatic Gain Control Scheme………………………………………….63 4.3 Clock Generator and IF Signal Comparator………………………………69 4.4 AGC Enable Circuit………………………………………………………71 4.5 AGC Digital Feedback Loop………………………………………………74 4.5.1 Digital Circuit Overview………………………………………….…74 4.5.2 Pre-decision Logic and Gain Control Logic…………………………76 4.6 Simulation Results…………………………………………………………79 4.7 Summary………………………………………………………………….82 Chapter 5 AGC-RF Front-End Implementation and Measurement Results…….………………………83 5.1 Measurement Results of Variable Gain RF Front-End……………………83 5.1.1 Overview of The Variable Gain RF Front-End ……………………..83 5.1.2 Measurement Setup…………………………………………………85 5.1.3 Measurement Results………………………………………………..89 5.2 AGC RF Front-End Integration…………………………………………101 5.2.1 Mixed-Mode and Post Simulation…………………………………102 5.2.2 Measurement Setup…………………………………………………105 5.3 Summary…………………………………………………………………106 Chapter 6 Conclusions and Future Works………….………….…107 BIBLOGRAPHY……………………………………………………108

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