簡易檢索 / 詳目顯示

回結果列表
研究生： 吳品昀
Wu, Pin-Yun
論文名稱： 正電壓轉負電壓之負壓產生器和具同相位自體參考電壓的負壓線性穩壓器
A Negative Voltage Generator with Positive Input and Negative Low-Dropout Voltage Regulator using Self-Generated Reference Voltage
指導教授： 徐永珍
Hsu, Klaus Yung-Jane
口試委員: 張彌彰
Chang, Mi-Chang
賴宇紳
Lai, Yu-Shen
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 中文
論文頁數： 50
中文關鍵詞： 負電壓 、負電荷泵 、線性穩壓器 、自體參考電壓 、直流-直流轉換器
外文關鍵詞： negative voltage, negative charge pump, low-dropout regulator, self-generated referenced voltage, DC-to-DC converter
相關次數： 點閱：2  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • 目前矽基半導體元件發展成熟，但隨著現在科技目標走向高頻、輕量與小體積，矽基半導體逐漸達到發展的臨界點。第三代半導體具有低能耗高效能的優點，在5G市場下能體現他們高頻下的穩定度和切換速度，未來的應用上將成為主流。第三代半導體中的氮化鎵(GaN)現在已廣泛使用在射頻及微波等領域，而最常見的氮化鎵元件主要為高電子遷移率電晶體(HEMT)，其需要一個正汲極電壓和一個負閘極電壓使其能操作在空乏層。然而目前所有的負壓產生器或供應大多為高電壓或是使用額外電源供應，無法滿足氮化鎵元件所需要的電壓範圍及SoC上的需求。

    為了實現這兩點目標，本篇碩士論文提出一個由正1.5V電壓轉為−1.5V電壓的負壓產生器，利用單一供應電壓產出的負電壓以滿足氮化鎵元件和系統單晶片的應用。為了使輸出的負電壓穩定，本次設計之負壓產生電路使用線性穩壓器(LDO)作為穩壓電路，利用LDO低電流低電壓及體積小的優點幫助輸出穩定、減少連波。而為了提供LDO參考電壓，本次設計利用不同級負電荷泵的輸出及電荷泵輸出電壓和LDO功率電晶體閘極電壓漣波同相位的特性來達到自體參考電壓和回授的機制，使得LDO即使不使用額外的負壓參考電壓，也能實現負壓產生器的輸出穩定。在模擬結果方面，本篇碩士論文提出一以180奈米製程設計之負電壓產生器，其在供應電壓為1.5V下能輸出−1.5V且漣波大小為960μV，操作於69.8MHz且在重載30kΩ的情況負載電流為50μA，電路消耗為1.33mW。在量測結果中，在供應電壓為1.5V並負載30kΩ的情況下輸出電壓為−1.495V，漣波13.5mV，時脈頻率為65.8MHz。

    As technology aims to decrease volume, increase frequency, and become light-weighted, though silicon-based transistor developed so far is so mature, it still reaches its limits and can’t break through. The third-generation semiconductor then take advantage of it, not only because of their low power consumption and high efficiency, but also their superior switching speed and stability under high frequency. GaN, as one of the third-generation semiconductor, has generally used in radio frequency and microwave technologies, and to operate GaN-based high electron mobility transistor (HEMT), it needs a negative gate voltage that ranges between −0.2V~−4V.

    In this thesis, a negative voltage generator with 1.5V input and −1.5V output is proposed. To stabilize output voltage and decrease ripple, the proposed negative voltage generator employs a low dropout regulator (LDO) at the end of the circuit as LDO is well-used in low voltage, low current, and small area applications. Meanwhile, to apply a reference voltage used in the error amplifier in LDO, a three-stage negative charge pump is proposed. Using the output of the second stage charge pump as self-reference voltage and featuring the same phase ripple of the negative charge pump outputs and the LDO power MOSFET gate voltage, the LDO can stabilize the negative voltage without additional power supply. In simulation results, supplying 1.5V input, the negative charge pump can reach −1.5V with only 960μV ripple, the clock frequency is 69.8MHz, maximum load current is 50μA when loading a 30kΩ resistor at the output and the whole circuit consumes 1.33mW power. In measurement results, the output of the circuit is −1.495V with 1.5V input when loading a 30kΩ resistor at the output, the output ripple is 13.5mV and the measured clock frequency is 65.8MHz.

    摘要 i Abstract ii 致謝 iii 圖目錄 vi 表目錄 viii 第一章 緒論 1 1.1 研究背景與動機 1 1.2 論文章節架構 4 第二章 文獻回顧 5 2.1 負電荷泵 5 2.1.1 傳統負電荷泵 5 2.1.2 交錯式反向負電荷泵 6 2.1.3 交叉耦合負電荷泵 6 2.1.4 交叉耦合PMOS閂式負電荷泵 7 2.2 線性穩壓器 8 2.2.1 輸出電壓差 9 2.2.2 線性調節率 10 2.2.3 輸出準確率 12 第三章 電路設計與架構 13 3.1 總電路架構 13 3.2 負壓LDO 13 3.3 負電壓產生器和負電荷泵 15 3.3.1 第一級負電荷泵 16 3.3.2 第二、三級負電荷泵 17 3.4 低壓定頻震盪器 21 3.5 非重疊時脈產生器 22 第四章 模擬與佈局 24 4.1 Pre-simulation 24 4.1.1 震盪頻率與時脈 24 4.1.2 電壓輸出 25 4.2 晶片佈局 27 4.3 Post-simulation 29 4.3.1 震盪頻率與時脈 29 4.3.2 電壓輸出表現 30 4.3.3 電路功耗 33 4.3.4 不同環境下之模擬結果 35 第五章 量測環境設計與結果 36 5.1 PCB設計 36 5.2 量測方法 37 5.2.1 量測儀器介紹 37 5.2.2 環境架設 38 5.3 量測結果及分析 38 第六章 總結與研究建議 44 6.1 總結 44 6.2 文獻比較 45 6.3 後續研究建議 46 6.3.1 非重疊時脈 46 6.3.2 自體參考電壓源 46 6.3.3 電路能量效率 48 參考文獻 49

    1. Khanna, D., et al., A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019. 66(9): p. 3423-3436.
    2. R. Laffont, J.R., P. Canet, R. Bouchakour and J. M. Mirabel, Decreasing EEPROM programming bias with negative voltage, reliability impact, in Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002). 2002: Bendor, France. p. 168-173.
    3. S. Ethier, M.S., E. M. Aboulhamid and M. El-Gamal, A ±9 V fully integrated CMOS electrode driver for high-impedance microstimulation, in 2009 52nd IEEE International Midwest Symposium on Circuits and Systems. 2009: Cancun, Mexico. p. 192-195.
    4. A. Rashidi, N.Y.a.A.M.S., Fully-Integrated, High-Efficiency, Multi-Output Charge Pump for High-Density Microstimulators, in 2018 IEEE Life Sciences Conference (LSC. 2018: Montreal, QC, Canada. p. 291-294.
    5. al, F.M.e., A Power-Efficient Hybrid Single-Inductor Bipolar-Output DC-DC Converter with Floating Negative Output for AMOLED Displays, in 2020 IEEE Custom Integrated Circuits Conference (CICC). 2020: Boston, MA, USA. p. 1-4.
    6. H. -J. Lee, H.-Y.K.a.H.-Y.C., Highly Integrated 2-Ch DC-DC Converter with Wide-Input Voltage Range for Wearable AMOLED Display, in 2020 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). 2020: Nagoya, Japan. p. 460-463.
    7. F. Boera, A.S., E. Bonizzoni and F. Maloberti, Design of a SIBO DC-DC Converter for AMOLED Display Driving, in 2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). 2018: Prague, Czech Republic. p. 109-112.
    8. Y. Tan, C.Z.a.G.W., A Fully-On-Chip Analog Low-Dropout Regulator With Negative Charge Pump for Low-Voltage Applications. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019. 66: p. 1361-1365.
    9. Y. -C. Huang, M.-D.K.a.C.-Y.L., Design of Negative High Voltage Generator for Biphasic Stimulator with SoC Integration Consideration. 2012 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2012: p. 29-32.
    10. R. Chebli, M.S.a.Y.S., A programmable positive and negative high-voltage DC-DC converter dedicated for ultrasonic applications, in 48th Midwest Symposium on Circuits and Systems. 2005: Covington, KY, USA. p. 679-682.
    11. DC-DC Conversion Without Inductors. 2009. https://pdfserv.maximintegrated.com/en/an/AN725.pdf.
    12. Jon Kraft, S.K. The Interleaved Inverting Charge Pump—Part 1: A New Topology for Low Noise Negative Voltage Supplies. 2020. https://www.analog.com/media/en/analog-dialogue/volume-54/number-4/the-interleaved-inverting-charge-pump-part-1.pdf.
    13. Jun Zhao, Kyung Ki Kim, and Y.-B. Kim, Negative high voltage DC-DC converter using a New Cross-coupled Structure. Journal of Integrated Circuits and Systems, 2015. 10: p. 158-165.
    14. Lee, C., Yim, T., & Yoon, H., A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM. Electronics, 2020. 9: p. 1769.
    15. Prasad, G. Power Management Circuits. 2015. DOI: 10.13140/RG.2.1.2873.1763.
    16. Lee, B.S., Understanding the Terms and Definitions of LDO Voltage Regulators. 1999. https://www.ti.com/lit/an/slva079/slva079.pdf?ts=1675208209230&ref_url=https%253A%252F%252Fwww.google.com%252F.
    17. Daga, E.R.a.J.-M., A PMOS-Switch based charge pump, allowing lost cost Implementation on a CMOS standard process. Proc. IEEE Eur. Conf. Solid-State Circuits, 2005: p. 77–80.
    18. P. Crepaldi, T.P.a.R.M., A CMOS Low Drop out Voltage Regulator, in 2010 International Conference on Microelectronics. 2010: Cairo, Egypt. p. 208-211.
    19. M. Kong, B.Z., H. Chen and X. Chen, A novel CMOS positive to negative voltage converter and regulator, in 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC). 2017: Hsinchu, Taiwan. p. 1-2.

    QR CODE