研究生: |
張蕙心 Chang, Hui-Hsin |
---|---|
論文名稱: |
藉由形成鍺化鈦在N型鍺上實現低接觸電阻之鍺技術研究 Enabling Low Contact Resistivity on n-Ge by Forming Ti Germanide for Ge Technology |
指導教授: |
巫勇賢
Wu, Yung-Hsien |
口試委員: |
李明昌
Lee, Ming-Chang 吳添立 Wu, Tian-Li |
學位類別: |
碩士 Master |
系所名稱: |
原子科學院 - 工程與系統科學系 Department of Engineering and System Science |
論文出版年: | 2017 |
畢業學年度: | 105 |
語文別: | 中文 |
論文頁數: | 63 |
中文關鍵詞: | 鍺化鈦 、N型鍺 、接觸電阻 、蕭特基能障高度 、鍺技術 、費米能階釘札 |
外文關鍵詞: | Titanium germanide, n type germanium |
相關次數: | 點閱:2 下載:0 |
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金屬於n型鍺上的費米能階釘札現象產生於大量的表面能態,也因為這個現象使得接觸金屬和n型鍺之間產生較大的蕭特基能障,而不受接觸金屬之金屬功函數所調變,這意味著發展高性能之Ge n-MOSFETs受極大的挑戰,較大的蕭特基能障會造成較高的接觸電阻以及對Ge n-MOSFETs會有不利的電特性影響,為了解決這個問題同時保持製程相容性,鍺化鈦(TiGex)的形成及電特性在此研究中被探討。
第一部分,鍺化鈦的形成是透過沉積鈦及氮化鈦於n型鍺上(鍺化物形成前磷摻雜)接著進行快速熱退火,而從鍺化鈦/n型鍺接面有2×1019 cm-3的磷濃度觀察到明顯的摻雜析離現象,透過形成鍺化鈦可以使得蕭特基能障由0.53 eV下降至0.22 eV,接觸電阻率由10-1 ohm-cm2被改善至1.53×10-5 ohm-cm2,為了持續減少接觸電阻率,在第二部分中我們藉由透過鍺化鈦附加的磷離子摻雜(鍺化物形成後磷摻雜)和後續的退火增強接面磷濃度,由於更明顯的摻雜析離效應,我們達到更好的蕭特基能障高度0.17 eV以及接觸電阻率3.69×10-6 ohm-cm2。
鍺化鈦的形成過程與目前的VLSI技術完美兼容且良好的接觸電阻率證明鍺化物具有成為小於7奈米技術的接觸金屬資格。
Fermi-level pinning for metal on n-type germanium (Ge) arising from a large amount of surface states represents a great challenge in developing high-performance Ge n-MOSFETs since it makes a large Schottky barrier between contact metal and n-type Ge, independent of the work function of contact metal. It is the large Schottky barrier that results in high contact resistance and adversely affects the electrical performance of Ge n-MOSFETs. To circumvent this issue while preserving the process compatibility, formation of titanium germanide (TiGex) and characterization of electrical performance were studied in this work.
In the first part, TiGex was formed by depositing Ti and TiN on n-type Ge (phosphorous implantation before germanide, IBG) followed by rapid thermal annealing and significant dopant segregation effect was observed with phosphorous (P) concentration of 2×1019 cm-3 at TiGex/n-type Ge interface. By forming TiGex, the Schottky barrier reduces from 0.53 eV to 0.22 eV while the contact resistivity improves from 10-1 Ω-cm2 to 1.53×10-5 Ω-cm2. To further decrease the contact resistivity, in the second part, interfacial P concentration was enhanced by additional P ion implantation through TiGex (phosphorous implantation after germanide, IAG) and a subsequent annealing. Due to more pronounced dopant segregation effect, better Schottky barrier height of 0.17 eV and contact resistivity of 3.69×10-6 ohm-cm2 were achieved.
The process to form TiGex is fully compatible with incumbent VLSI technology and the good contact resistivity attests to the eligibility of the germanide as the contact material for sub-7 nm technology.
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