在MOSFET的超薄介電層以矽製成的微電子元件時代的關鍵元件，所述二氧化矽閘極氧化物到了設備的性能和縮放的關鍵。以SiO2為基礎的閘極氧化物的物理厚度接近〜2奈米，一些關鍵的電介質參數退化：閘極漏電流，多晶矽閘極氧化層擊穿，和通道遷移率。解決的辦法是與具有更高介電常數（高k）的材料代替傳統的二氧化矽閘極氧化物。高k值絕緣體可以生長為相同的（或更薄）等效電氧化層厚度（EOT）物理上更厚，從而提供顯著閘極漏電流減少。高k材料被推出，取代SiO2，來解決閘極漏電問題。即使相當大的性能改進和閘極漏電減少已經實現，高κ材質元件帶來新的元件可靠度挑戰，例如正和負偏壓溫度不穩定性（P / NBTI）和熱載流子注入（HCI）需要進行研究。 本文提出一種實現在堆疊式TiN /HfO2 /SiO2的新型28奈米CMOS邏輯高k /金屬閘（HK / MG）技術的可靠性影響。在第2章中，運用快速運作的量測技術在高k電介質中，以減少由於電荷被捕獲/脫逃。第3章提出P / NBTI和HCI在先進HK / MG介質CMOSFET之間退化特性的相關性研究。一種可靠性的最佳化製程研究，像是氧的敏感度和閘極疊層的厚度效果將在第4章進行討論。在第5章，針對隨機電報式訊號RTS幅度分佈之電流波動，通過統計分析和使用RTS來估算元件壽命。在第6章呈獻交流式高溫壽命AC HTOL 測試和目前的各種元件退化機制，如NBTI，PBTI和HCI在6T型（6個電晶體型）靜態隨機存取記憶體(SRAM)的研究。且探討了氮化退火（PNA）可改進PBTI的可靠性，最後，第7章是結論。

The ultra-thin gate dielectrics in MOSFETs remain the key element in conventional silicon-based microelectronic devices era, the SiO2 gate oxide has played a critical role in device performance and scaling. As the physical thickness of SiO2-based gate oxides approaches ~2 nm, some key dielectric parameters degrade: gate leakage current, oxide breakdown from the poly-silicon gate electrode, and channel mobility. The solution is to replace conventional SiO2 gate oxides with a material having higher permittivity (high-k). High-k insulators can be grown physically thicker for the same (or thinner) equivalent electrical oxide thickness (EOT), thus offering significant gate leakage reduction. High-k material is introduced to replace SiO2 to solve the gate leakage problem. Even though considerable performance improvement and gate leakage reduction have been achieved, new reliability challenges of high-κ devices such as the positive and negative bias temperature instability (P/NBTI) and hot carrier injection (HCI) need to be investigated.
This dissertation presents an impact of reliability on a novel 28 nm CMOS logic high-k/metal-gate (HK/MG) technologies realized by stacking TiN/HfO2/SiO2. The fast transient measurement technique to reduce the post-stress transient effect due to charge trapping/detrapping in high-k dielectric is demonstrated in Chapter 2. The correlation of degradation characteristics between the P/NBTI and HCI in advanced HK/MG dielectric CMOSFET is proposed in Chapter 3. Oxygen sensitivity and the thickness effect for the optimized gate stack is discussed in Chapter 4. Chapter 5 focuses on current fluctuations in HK gate dielectric MOSFETs due to RTS amplitude distribution, the carrier lifetime estimated with RTS by using graphical extrapolation is discussed. An overview of various aging mechanisms such as NBTI, PBTI, and HCI in the 6T SRAM by AC HTOL stress is presented in Chapter 6, and a post nitridation anneal (PNA) treatment that improves the PBTI reliability is also presented in Chapter 6. Finally, conclusions are made in Chapter 7.

Chapter 1

[1.1] G. D. Wilk, R. M. Wallace, and J. M. Anthony, ‘‘High-K Gate Dielectrics: Current Status and Materials Properties Considerations,’’ J. Appl. Phys. Vol. 89, pp. 5243, 2001.
[1.2] A. Callegari, E. Cartier, M. Gribelyuk, H. F. Okorn- Schmidt, and T. Zabel, ‘‘Physical and Electrical Characterization of Hafnium Oxide and Hafnium Silicate Sputtered Films,’’ J. Appl. Phys. Vol. 90, pp. 6466, 2001.
[1.3] E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn-Schmidt, C. D’Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L. Ragnarsson, P. Ronshein, K. Rim, R. J. Fleming, A. Mocuta, and A. Ajmera, ‘‘Ultrathin High-j Gate Stacks for Advanced CMOS Devices,’’ IEDM Tech. Digest, pp. 451-454, 2001.
[1.4] M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo, ‘‘Application of HfSiON as a Gate Dielectric Material,’’ Appl. Phys. Lett. Vol. 80, p. 3183, 2002.
[1.5] E. P. Gusev, C. Cabral, M. Copel, C. D’Emic, and M. Gribelyuk, ‘‘Ultrathin HfO2 Films Grown on Silicon by Atomic Layer Deposition for Advanced Gate Dielectrics Applications,’’ Microelectron. Eng., Vol. 69, p. 145, 2003.
[1.6] L. Kang, B. H. Lee, W.-J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi, and J. C. Lee, ‘‘Electrical Characterization of Highly Reliable Ultrathin Hafnium Oxide Gate Dielectric,’’ IEEE Electron Device Lett. Vol. 21, p. 181, 2000.
[1.7] G. D. Wilk, R. M. Wallace, and J. M. Anthony, ‘‘Hafnium and Zirconium Silicates for Advanced Gate Dielectrics,’’ J. Appl. Phys. Vol. 87, p. 484 (2000).
[1.8] M. S. Akbar, S. Gopalan, H. J. Cho, K. Onishi, R. Choi, R. Nieh, C. S. Kang, Y. H. Kim, J. Han, S. Krishnan, and J. C. Lee, ‘‘High-Performance TaN/HfSiON/Si MOS Structures Prepared by NH3 Post-Deposition Anneal,’’ Appl. Phys. Lett. Vol. 82, p. 1757, 2003
[1.9] S. Zafar, A. Kumar, E. P. Gusev, and E. Cartier, ‘‘Threshold Voltage Instabilities in High-j Gate Dielectric Stacks,’’ IEEE Trans. Device & Mater. Reliabil. Vol. 5, p. 45, 2005.
[1.10] E. P. Gusev, C. P. D’Emic, S. Zafar, and A. Kumar, “Charge trapping and detrapping in HfO2 high- gate stacks,” Microelectron. Eng., vol. 72, p. 273, 2004.
[1.11] S. Zafar, S. Callegari, V. Narayanan, and S. Guha, “Impact of moisture on charge trapping and flatband voltage in Al2O3 gate dielectric films,” Appl. Phys. Lett., vol. 81, p. 2608, 2002.
[1.12] S. Zafar, A. Callegari, E. P. Gusev, and M. V. Fischetti, “Charge trapping in high-k gate dielectric stacks,” in IEDM Tech. Dig., 2002, pp. 517–520.
[1.13] S. Zafar, A. Callegari, E. P. Gusev, and M. V. Fischetti, “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks,” J. Appl. Phys., vol. 93, pp. 9298–9309, 2003.
[1.14] W. J. Zhu, T. P. Ma, S. Zafar, and T. Tamagawa, “Charge trapping in ultrathin hafnium oxide,” IEEE Electron Device Lett., vol. 23, no. 10, pp. 597–599, Oct. 2002.
[1.15] A. Kumar, T. H. Ning, M. V. Fischetti, and E. P. Gusev, “Hot-carrier charge trapping and reliability in high- dielectrics,” in VLSI Symp. Tech. Dig., 2002, p. 152.
[1.16] A. Kumar, M. V. Fischetti, T. H. Ning, and E. P. Gusev, “Hot-carrier charge trapping and trap generation in HfO2 and Al2O3 field-effect transistors,” J. Appl. Phys., vol. 94, p. 1728, 2003.
[1.17] J. R. Chavez, R. A. B. Devine, and L. Koltunski, “Evidence for hole and electron trapping in plasma deposited ZrO2 thin films,” J. Appl. Phys., vol. 90, p. 4284, 2001.
[1.18] R. Ludeke, M. T. Cuberes, and E. Cartier, “Local transport and trapping issues in Al2O3 gate oxide structures,” Appl. Phys. Lett., vol. 76, p. 2886, 2001.
[1.19] S. Zafar, B. H. Lee, and J. Stathis, “ Evaluation of NBTI in HfO gatedielectric stacks with tungsten gates,” IEEE Electron Device Lett., vol. 23, no. 3, pp. 153–155, Mar. 2004.
[1.20] S. Zafar, B. H. Lee, J. Stathis, and T. Ning, “A model for negative bias temperature instability (NBTI) in oxide and high-k pFETs,” in Symp. VLSI Technology Tech. Dig., 2004, pp. 208–209.
[1.21] E. P. Gusev and C. D’Emic, “Charge detrapping in HfO2 high- gate dielectric stacks,” Appl Phys. Lett., vol. 83, p. 5223, 2003.
[1.22] S. Tsujikawa, T. Mine, K. Wanatabe, Y. Shimamoto, R. Tsuchiya, K. Onishi, T. Onai, J. Mi, N. Novkovski, N. Yugami, and S. Kimura, “Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics,” in Proc. Int. Rel. Phys. Symp., 2003, pp. 183–188.
[1.23] S. Guha, E. P. Gusev, H. Okorn-Schmidt, M. Copel, L.-A˚ . Ragnarsson, and N. Bojarczuk, ‘‘High Temperature Stability of Al2O3 Dielectrics on Si: Interfacial Metal Diffusion and Mobility Degradation,’’ Appl. Phys. Lett. 81, 2956, 2002.
[1.24] M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, ‘‘Effective Electron Mobility in Si Inversion Layers in Metal– Oxide–Semiconductor Systems with a High-Kappa Insulator: The Role of Remote Phonon Scattering,’’ J. Appl. Phys. 90, 4587–4608, 2001.
[1.25] Z. Ren, M. Fischetti, E. P. Gusev, E. Cartier, and M. Chudzik, ‘‘Inversion Channel Mobility in High-j High Performance MOSFETs,’’ Symp. VLSI Technol., p. 793, 2003.
[1.26] M. M. Frank, V. K. Paruchuri, V. Narayanan, N. Bojarczuk, B. Linder, S. Zafar, E. A. Cartier, E. P. Gusev, P. C. Jamison, K.-L. Lee, M. L. Steen, M. Copel, S. A. Cohen, K. Maitra, X. Wang, P. M. Kozlowski, J. S. Newbury, D. R. Medeiros, P. Oldiges, S. Guha, R. Jammy, M. Ieong, and G. Shahidi, ‘‘Poly-Si/High-k Gate Stacks with Near-Ideal Threshold Voltage and Mobility,’’ IEEE VLSI–TSA–Tech, International Symposium on VLSI Technology, 2005, pp. 97–98.
[1.27] N. Raghavan, K.L. Pey and X. Li, “Detection of high-κ and interfacial layer breakdown using the tunneling mechanism in a dual layer dielectric stack”, Applied Physics Letters, Vol. 95, p. 222903, 2009.
[1.28] V.L. Lo, K.L. Pey, C.H. Tung and D.S. Ang, “A critical voltage triggering irreversible gate dielectric degradation”, in Proc. Int. Rel. Phys. Symp., pp.576-577, (2007).
[1.29] F. Crupi, T. Kauerauf, R. Degraeve, L. Pantisano and G. Groeseneken, “ A novel methodology for sensing the breakdown location and its application to the reliability study of ultrathin Hf-silicate gate dielectrics”, IEEE Transactions on Electron Devices, Vol. 52, No. 8, pp.1759-1765, (2005).
[1.30] J. Sune, E.Y. Wu, D. Jimenez and W.L. Lai, “Statistics of soft and hard breakdown in thin SiO2 gate oxides”, Microelectronics Reliability, Vol. 43, pp.1185-1192, (2003).
[1.31] R. Ranjan, K.L. Pey, C.H. Tung, L.J. Tang, G. Groeseneken, L.K. Bera and S. De Gendt, “A comprehensive model for breakdown mechanism in HfO2 high-κ gate stacks”, IEEE International Electron Device Meeting (IEDM), pp.725-728, (2004).
[1.32] Y.H. Kim, K. Onishi, C.S. Kang, H.J. Cho, R. Nieh, S. Gopalan, R. Choi, J. Han, S. Krishnan and J.C. Lee, “Area dependence of TDDB characteristics for HfO2 gate dielectrics”, IEEE Electron Device Letters, Vol. 23, No. 10, pp.594-596, 2002.
[1.33] N. Raghavan, K.L. Pey, W.H. Liu, X. Wu and X. Li, “Unipolar recovery of dielectric breakdown in fully silicided high-κ gate stack devices and its reliability implications”, Applied Physics Letters, Submitted, 2010.
[1.34] G. Bersuker, N. Chowdhury, C. Young, D. Heh, D. Misra and R. Choi, “Progressive breakdown characteristics of high-κ/metal gate stacks”, in Proc. Int. Rel. Phys. Symp., pp.49-54, 2007.
[1.35] P. A. Stolk, F. P. Widdershoven, and D. B. M. Klaassen, "Modeling statistical Mean dopant fluctuations in MOS transistors" IEEE Trans. on Elec. Dev., Vol. 45, no. 9, pp 1960-1971, Sept. 1998.
[1.36] T-H Yu, T. Ohtou, K-M Liu, W-Y Chen, Y-P Hu, C-F Cheng, and Y-M Sheu, "Modeling and Optimization of Variability in Highk/Metal-Gate MOSFETs," in Simulation of Semiconductor Processes and Devices, pp. 9-11, Sept. 2009.
[1.37] Y-Y Chiu , Y Li, and H-W Cheng, " Correlation between Interface Traps and Random Dopants in Emerging MOSFETs," in Simulation of Semiconductor Processes and Devices, pp. 291-294, Sept. 2011.

Chapter 2

[2.1] M. Cho, M. Aoulaiche, R. Degraeve, B. Kaczer, J. Franco, T. Kauerauf, P. Roussel, L. Å. Ragnarsson, J. Tseng, T. Y. Hoffmann, and G. Groeseneken, “Positive and negative bias temperature instability on sub-nanometer eot high-K MOSFETs,“ in Proc. Int. Rel. Phys. Symp., 2010, pp. 1095-1098.
[2.2] S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Kavalieros, K. Kuhn, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, and J. Wiedemer, “BTI Reliability of 45 nm High-K + Metal-Gate Process Technology”, in Proc. Int. Rel. Phys. Symp., 2008, pp. 352-357.
[2.3] K. Zhao, J. Stathis, E. Cartier, M. Wang, H. Jagannathan, and S. Zafar, “Detailed Study of Fast Transient Relaxation of Vt Instability in HKMG nFETs”, in Proc. Int. Rel. Phys. Symp., 2012, pp. XT.14.1-XT.14.4.
[2.4] N. Goel, S. Mukhopadhyay, N. Nanaware, S. De, R. K. Pandey, K. V. R. M. Murali, and S. Mahapatra, “A Comprehensive DC/AC Model for Ultra-Fast NBTI in Deep EOT Scaled HKMG p-MOSFETs”, in Proc. Int. Rel. Phys. Symp., 2014, pp. 6A.4.1 -6A.4.12.
[2.5] A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra, and M. A. Alam, “Recent issues in negative-bias temperature instability: initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation” ,IEEE Trans Electron Dev., Vol. 54, no. 9, pp. 2143–2154, 2007.
[2.6] T. Aichinger, M. Nelhiebel, T. Grasser, ‘‘On the temperature dependence of NBTI recovery,’’ Microelectron Reliab., Vol. 48, pp. 1178–1184, 2008.
[2.7] H. Reisinger, O. Blank, W. Heinrigs, A. Mühlhoff, W. Gustin, and C. Schlünder, “Analysis of NBTI Degradation- and Recovery-Behavior Based on Ultra Fast VT-Measurements”, in Proc. Int. Rel. Phys. Symp., 2006, pp. 448-453.
[2.8] C. D. Young, Y. Zhao, D. Heh, R. Choi, B. H. Lee, and G. Bersuker, “Pulsed Id–Vg Methodology and Its Application to Electron-Trapping Characterization and Defect Density Profiling”, IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1322–1329, June 2009.
[2.9] E. N. Kumar, V. D. Maheta, S. Purawat, A. E. Islam, C. Olsen, K. Ahmed, M. A. Alam and S. Mahapatra, ‘‘Material Dependence of NBTI Physical Mechanism in Silicon Oxynitride (SiON) p-MOSFETs: A Comprehensive Study by Ultra-Fast On-The-Fly (UF-OTF) IDLIN Technique,’’ IEDM Tech. Digest, pp. 809-812 2007.
[2.10] Agilent Technologies Inc. Agilent B1530A waveform generator/fast measurement unit user’s guide; 2012.

Chapter 3

[3.1] G. D. Wilk, R. M. Wallace, and J. M. Anthony, ‘‘High-j Gate Dielectrics: Current Status and Materials Properties Considerations,’’ J. Appl. Phys. 89, 5243 (2001).
[3.2] A. Callegari, E. Cartier, M. Gribelyuk, H. F. Okorn- Schmidt, and T. Zabel, ‘‘Physical and Electrical Characterization of Hafnium Oxide and Hafnium Silicate Sputtered Films,’’ J. Appl. Phys. 90, 6466 (2001).
[3.3] D. C. Gilmer, R. Hegde, R. Cotton, J. Smith, L. Dip, R. Garcia, V. Dhandapani, D. Triyoso, D. Roan, A. Franke, R. Rai, L. Prabhu, C. Hobbs, J. M. Grant, L. La, S. Samavedam, B. Taylor, H. Tseng, and P. Tobin, ‘‘Compatibility of Silicon Gates with Hafnium-Based Gate Dielectrics,’’ Microelectron. Eng. Vol. 69, p.138, 2003.
[3.4] E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn-Schmidt, C. D’Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L. Ragnarsson, P. Ronshein, K. Rim, R. J. Fleming, A. Mocuta, and A. Ajmera, ‘‘Ultrathin High-j Gate Stacks for Advanced CMOS Devices,’’ IEDM Tech. Digest, pp. 451-454 ,2001.
[3.5] M. S. Akbar, S. Gopalan, H. J. Cho, K. Onishi, R. Choi, R. Nieh, C. S. Kang, Y. H. Kim, J. Han, S. Krishnan, and J. C. Lee, ‘‘High-Performance TaN/HfSiON/Si MOS Structures Prepared by NH3 Post-Deposition Anneal,’’ Appl. Phys. Lett. Vol. 82, p. 1757, 2003.
[3.6] K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H. Watanabe, T. Tatsumi, and Y. Mochizuki, ‘‘Dual Workfunction Ni-Silicide/HfSiON Gate Stacks by Phase-Controlled Full-Silicidation (PC-FUSI) Technique for 45nm-Node LSTP and LOP Devices,’’ IEDM Tech. Digest, pp. 91–94, 2004.
[3.7] M. R. Visokay, J. J. Chambers, A. L. P. Rotondaro, A. Shanware, and L. Colombo, ‘‘Application of HfSiON as a Gate Dielectric Material,’’ Appl. Phys. Lett. Vol. 80, 3183, 2002.
[3.8] E. P. Gusev, C. Cabral, M. Copel, C. D’Emic, and M. Gribelyuk, ‘‘Ultrathin HfO2 Films Grown on Silicon by Atomic Layer Deposition for Advanced Gate Dielectrics Applications,’’ Microelectron. Eng. Vol. 69, p. 145, 2003.
[3.9] B. H. Lee, L. Kang, W.-J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J. C. Lee, ‘‘Ultrathin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate Dielectric Application,’’ IEDM Tech. Digest, pp. 133–136, 1999.
[3.10] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo”, Review on High-k Dielectrics Reliability Issues,” IEEE Trans. Device and Mater. Rel., vol. 5, no. 1, pp. 5-19, Mar. 2005.
[3.11] G. Bersuker, B. H. Lee, and H. R. Huff, “Novel dielectric materials for future transistor generations,” Int. J. High Speed Electron. Syst., vol. 16, no. 1, pp. 221–239, Mar. 2006.
[3.12] S. Zafar, Y. H. Kim, V. Narayanan, C. Cabral Jr., V. Paruchuri, B. Doris, J. Stathis, A. Callegari, and M. Chudzik, “A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates,” in VLSI Symp. Tech. Dig., 2006, pp. 23-25.
[3.13] S. Zafar, A. Kumar, E. P. Gusev, and E. Cartier, ‘‘Threshold Voltage Instabilities in High-k Gate Dielectric Stacks,’’ IEEE Trans. Device & Mater. Reliabil. Vol. 5, p. 45, 2005.
[3.14] S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Kavalieros, K. Kuhn, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, and J. Wiedemer, “BTI Reliability of 45 nm High-K + Metal-Gate Process Technology”, in Proc. Int. Rel. Phys. Symp., 2008, pp. 352-357.
[3.15] M. Cho, M. Aoulaiche, R. Degraeve, B. Kaczer, J. Franco, T. Kauerauf, P. Roussel, L. Å. Ragnarsson, J. Tseng, T. Y. Hoffmann, and G. Groeseneken, “Positive and negative bias temperature instability on sub-nanometer eot high-K MOSFETs,“ in Proc. IRPS Symp., 2010, pp. 1095-1098.
[3.16] S. Krishnan, V. Narayanan, E. Cartier, D. Ioannou, K. Zhao, T. Ando, U. Kwon, B. Linder, J. Stathis, and M. Chudzik, “Bias Temperature Instability in High-κ/Metal Gate Transistors – Gate Stack Scaling Trends,” in Proc. IRPS Symp., 2012, pp. 5A.1.1-5A.1.6.M.
[3.17] D. Ioannou, S. Mittl, and G. La Rosa, “Positive Bias Temperature Instability effects in nMOSFETs with HfO2/TiN gate stacks,” IEEE Trans. Device Mater. Rel., vol. 9, no. 2, pp. 128-134, 2009.
[3.18] E. Cartier and A. Kerber, “Stress-induced leakage current and defect generation in nFETs with HfO2/TiN gate stacks during positive-bias temperature stress,” in Proc. Int. Rel. Phys. Symp., 2009, pp. 486-492.
[3.19] C. L. Hinkle, R. V. Galatage, R. A. Chapman, E. M. Vogel, H. N. Alshareef, C. Freeman, E. Wimmer, H. Niimi, A. Li-Fatou, J. B. Shaw, and J. J. Chambers, “Interfacial Oxygen and Aitrogen Induced Dipole Formation and Vacancy Passivation for Increased Effective Work Functions in TiN/HfO2 Gate Stacks,” Appl. Phys. Lett. vol. 96, pp. 103502, 2010.
[3.20] E. Cartier, M. Hopstaken, and M. Copel, “Oxygen Passivation of Vacancy Defects in Metal-Nitride Gated HfO2/SiO2/Si Devices,” Appl. Phys. Lett. vol. 95, pp. 042901, 2009.
[3.21] A. T. Krishnan, C. Chancellor, S. Chakravarthi, P. E. Nicollian, V. Reddy, A. Varghese, R. B. Khamankar, S. Krishnan, “Material Dependence of Hydrogen Diffusion: Implications for NBTI Degradation,” in IEDM Tech. Dig., 2005, pp. 691-694.
[3.22] C. L. Chen, Y. M. Lin. C. J. Wung. K. Wu, “A New Finding on NBTI Lifetime Model and an Investigation on NBTI Degradation Characteristic for 1.2nm Ultra Thin Oxide,” in Proc. Int. Rel. Phys. Symp., 2005, pp. 704-705.
[3.23] G. Krause, M. F. Beug, R. Ferretti, S. Prasad, K. R. Hofmann, “High-Field Degradation of Poly-Si Gate p-MOS and n-MOS Devices With Nitrided Oxides,” IEEE Trans. Device Mater. Rel., vol. 6, no. 3, pp. 473-478, 2006.
[3.24] S. Baba, A. Kita and J. Ueda, “Mechanism of hot carrier induced degradation in MOSFET's,” in IEDM Tech. Dig., 1986, pp. 734-737.
[3.25] H. Wang". M. Davis. H. De. S. Bibyk*. Y. N.-Cohen, “Transient hot-electron effect on n-channel device degradation (MOSFETs),” in IEDM Tech. Dig., 1989, pp. 79-82.
[3.26] S. A. Kim, B. Menberu, and J. E. Chung, “A New Algorithm for NMOS AC Hot-Carrier Lifetime Prediction Based on the Dominant Degradation Asymptote,” in Proc. IEEE Int. Reliab. Phys. Symp., 281-288, 1996.
[3.27] G. T. Sasse, J. Bisschop, “The Hot Carrier Degradation Rate Under AC Stress,” in Proc. IEEE Int. Reliab. Phys. Symp., 830-834, 2010.
[3.28] Y. M. Randriamihaja, A. Zaka, V. Huard, M. Rafik, D. Rideau, D. Roy, “MOSFET's hot carrier degradation characterization and modeling at a microscopic scale,” in Proc. IEEE Int. Reliab. Phys. Symp., XT.5.1-XT.5.3, 2011.
[3.29] A. Bravaix, Y. M. Randriamihaja, “Impact of the gate-stack change from 40nm node SiON to 28nm High-K Metal Gate on the Hot-Carrier and Bias Temperature damage,” in Proc. IEEE Int. Reliab. Phys. Symp., 2D.6.1-2D.6.9, 2013.
[3.30] P. Chaparala, J.s Shibley and P. Lim, “Threshold Voltage Drift in PMOSFETS due to NBTI and HCI,” in Int. Reliab. Works., 2000, pp. 95-97.
[3.31] C.-H. Jeon. S.-Y. Kim, H.-S. Kim, C.-B. Rim, “The Impact of NBTI and HCI con Deep Sub-micron PMOSFETs' Lifetime,” in IEEE Int. Reliab. Works., 2002, pp. 130-132.
[3.32] E. Amat, R. Rodríguez, M. Nafría and X. Aymerich, “New insights into the wide ID range Channel HotCarrier degradation in high-k based devices,” in Proc. IEEE Int. Reliab. Phys. Symp., 1028-1032, 2009.
[3.33] G. L. Rosa, F. Guarin, S. Rauch, A. Acovic, J. Lukaitis, E. Crabbe, “NBTI-channel hot carrier effects in PMOSFETs in advanced CMOS technologies,” in Proc. IEEE Int. Reliab. Phys. Symp., 282-286, 1997.
[3.34] H. Aono, E. Murakami, K. Ohyama, *K. Makabe, K. Kuroda, K. Watanabe, H. Ozaki, K.Yanagisawa, K. Kuhota, and Y.Ohji, “NBT-induced hot carrier (HC) effect: positive feedback mechanism in p-MOSFET's degradation,” in Proc. IEEE Int. Reliab. Phys. Symp., 79-85, 2002.
[3.35] Y. Mitani, S. Fukatsu, D. Hagishima, and K. Matsuzawa, “Separation of NBTI component from channel hot carrier degradation in pMOSFETs focusing on recovery phenomenon,” in IEEE IC Design & Technology, 2011, pp. 1-4.
[3.36] X. Federspiel, M. Rafik, D. Angot, F. Cacho, D. Roy, “Interaction between BTI and HCI degradation in High-K devices,” in Proc. IEEE Int. Reliab. Phys. Symp., XT.9.1-XT.9.4, 2013.
[3.37] CHENMING HU, and SIMON C. TAM, “Hot-Electron-induced MOSFET Degradation-Model, Monitor, and Improvement”, IEEE Journal Solid-State Circuits, pp.295-305, 1985.
[3.38] B. Doyle, and M. Dourcerie, “Interface State Creation and Charge Trapping in the Medium-to-High Gate Voltage Range ( Vd/2 ≥ Vg ≥ Vd) During Hot-Carrier Stressing of n-MOS Transistors”, IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2042–2048, Aug. 2012.

Chapter 4

[4.1] M. Dai, J. Liu, D. Guo, S. Krishnan, J. F. Shepard, P. Ronsheim, U. Kwon, S. Siddiqui, R. Krishnan, Z. Li, K. Zhao, J. Sudijono, and M. P. Chudzik, “A Novel Atomic Layer Oxidation Technique for EOT Scaling in Gate-Last High-κ/Metal Gate CMOS Technology,” in IEDM Tech. Dig., 2011, pp. 28.5.1- 28.5.4.
[4.2] C. K. Chiang, J. C. Chang, W. H. Liu, C. C. Liu, J. F. Lin, C. L. Yang , and J. Y. Wu, “A Comparative Study of Gate Stack Material Properties and Reliability Characterization in MOS Transistors with Optimal ALD Zirconia Addition for Hafina Gate Dielectric,” in Proc. IEEE Int. Reliab. Phys. Symp., GD.3.1- GD.3.4, 2012.
[4.3] S. Zafar, M. Yang, E. Gusev, A. Callegari, J. Stathis, T. Ning, R. Jammy, and M. Ieong, “A comparative study of NBTI as a function of Si substrate orientation and gate dielectrics (SiON and SiON/HfO2),” in IEEE Int. Symp. VLSI Technol., 2005, pp. 128–129.
[4.4] S. Zafar, A. Kumar, E. Gusev, and E. Cartier, “Threshold voltage instabilities in high-κ gate dielectric stacks,” IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 45–64, Mar. 2005.
[4.5] G. Ribes, M. Rafik, and D. Roy, “Reliability issues for nano-scale CMOS dielectrics,” Microelectron. Eng., vol. 84, no. 9, pp. 1910– 1916, 2007.
[4.6] A. Kerber and E. A. Cartier, “Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks,” IEEE Trans. Device and Mater. Rel., vol. 9, no. 2, pp. 147-162, June 2009.
[4.7] M. Aoulaiche, B. Kaczer, M. Cho, M. Houssa, R. Degraeve, T. Kauerauf, A. Akheyar, T. Schram, Ph. Roussel, H. E. Maes, T. Hoffmann, S. Biesemans, and G. Groeseneken, “Positive and negative bias temperature instability in La2O3 and Al2O3 capped high-k MOSFETs,” in Proc. IEEE IRPS, 2009, pp. 1014–1018.
[4.8] B. Kaczer, A. Veloso, M. Aoulaiche, and G. Groeseneken, “Signifi- cant reduction of positive bias temperature instability in high-k/metalgate nFETs by incorporation of rare earth metals,” Microelectron. Eng., vol. 86, no. 7–9, pp. 1894–1896, Jul.–Sep. 2009.
[4.9] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks,” J. Appl. Phys., vol. 93, no. 11, pp. 9298–9303, Jun. 2003.
[4.10] V. Huard, C. Parthasarathy, N. Rallet, C. Guerin, M. Mammase, D. Barge, and C. Ouvrard, “New characterization and modeling approach for NBTI degradation from transistor to product level,” in IEDM Tech. Dig., 2007, pp. 797–800.
[4.11] M. A. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation,” Microelectron. Reliab., vol. 45, no. 1, pp. 71–81, Jan. 2005.
[4.12] N. Tega, H. Miki, Z. Ren, C. P. D’Emic, Y. Zhu, D. J. Frank, J. Cai, M. A. Guillorn, D.-G. Park, W. Haensch, and K. Torii, “Reduction of Random Telegraph Noise in High-κ / Metal-gate Stacks for 22 nm Generation FETs,” in IEDM Tech. Dig., 2009, pp. 1-4.
[4.13] K. Lee, M. Frank, V. Paruchuri, E. Cartier, B. Linder, N. Bojarczuk, X. Wang, J. Rubino, M. Steen, P. Kozlowski, J. Newbury, E. Sikorski, P. Flaitz, M. Gribelyuk, P. Jamison, G. Singco, V. Narayanan, S. Zafar, S. Guha, P. Oldiges, R. Jammy, and M. Ieong, “Poly-Si/AlN/HfSiO stack for ideal threshold voltage and mobility in sub-100 nm MOSFETs,” in VLSI Symp. Tech. Dig., 2006, pp. 160–161.
[4.14] V. Narayanan, V. K. Paruchuri, E. Cartier, B. P. Linder, N. Bojarczuk, S. Guha, S. L. Brown, Y. Wang, M. Copel, and T. C. Chen, “Recent advances and current challenges in the search for high mobility bandedge high-k/metal gate stacks,” Microelectron. Eng., vol. 84, no. 9/10, pp. 1853–1856, Sep. 2007.
[4.15] K. Joshi, S. Mukhopadhyay, N. Goel and S. Mahapatra, “A Consistent Physical Framework for N and P BTI in HKMG MOSFETs,” in Proc. IEEE Int. Reliab. Phys. Symp., 2012, pp. 5A.3.1-5A.3.10.
[4.16] H. Arimura, L.-Å. Ragnarsson, T. Schram, J. Albert, B. Kaczer, R. Degraeve, E. Bury*, M. Aoulaiche, T. Kauerauf, A. Thean, N. Horiguchi, and G. Groeseneken, “Guidelines for reducing NBTI based on its correlation with effective work function studied by CV-BTI on high-k first MOS capacitors with slant-etched SiO2”, in Proc. IEEE Int. Reliab. Phys. Symp., 2014, pp. 3C.4.1 - 3C.4.6.
[4.17] M. Cho, J.-D. Lee, M. Aoulaiche, B. Kaczer, P. Roussel, T. Kauerauf, Ro. Degraeve, J. Franco, L.-Å. Ragnarsson, and G. Groeseneken, “Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices,” IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2042–2048, Aug. 2012.
[4.18] A. Neugroschel, G. Bersuker, R. Choi, and B. H. Lee”, Effect of the Interfacial SiO2 Layer in High-k HfO2 Gate Stacks on NBTI,” IEEE Trans. Device and Mater. Rel., vol. 8, no. 1, pp. 47-61, Mar. 2008.
[4.19] M. Sato, T. Aoyama, K. Sekine, T. Yamaguchi, I. Hirano, K. Eguchi, Y. Tsunashima, “Effects of Nitrogen Concentration and Poste-treatment on Reliability of HfSiON Gate Dielectrics in Inversion States,” Jpn. J. Appl. Phys., vol. 45, no. 4B, 2006, p. 2949-2953.
[4.20] S. J. Wang and J. W. Chai, Y. F. Dong, Y. P. Feng, N. Sutanto, J. S. Pan and A. C. H. Huan, “Effect of nitrogen incorporation on the electronic structure and thermal stability of HfO2 gate dielectic,” Appl. Phys. Lett. , 88, 192103, 2006.
[4.21] K. T. Lee, H. Kim, J. Park and J. Park, “Gate Stack Process Optimization for TDDB Improvement in 28nm High-k/Metal Gate nMOSFETs,” in Proc. IEEE Int. Reliab. Phys. Symp., 2012, pp. GD.2.1-GD.2.4.
[4.22] L. Wu, H. Y. Yu, X. Li, K. L. Pey, J. S. Pan, J. W. Chai, Y. S. Chiu, C. T. Lin, J. H. Xu, H. J. Wann, X. F. Yu, D. Y. Lee, K. Y. Hsu, and H. J. Tao,”Thermal stability of TiN metal gate prepared by atomic layer deposition or physical vapor deposition on HfO2 high-K dielectric,” in Appl. Phys. Lett., vol. 96, no. 11, pp. 113510-113510-3, Mar. 2010.
[4.23] L. Wu, H. Y. Yu, X. Li, K. L. Pey, K. Y. Hsu, H. J. Tao, Y. S. Chiu, C. T. Lin, J. H. Xu, and H. J. Wan, “Investigation of ALD or PVD (Ti-rich vs. N-rich) TiN Metal Gate Thermal Stability on HfO2 High-K”, in VLSI-TSA, 2010, pp. 90-91.
[4.24] C.-L. Chen and Y.-C. King, "TiN Metal Gate Electrode Thickness Effect on BTI and Dielectric Breakdown in HfSiON-Based MOSFETs," IEEE Trans. Electron Device, vol. 58, no. 11, 2011, pp. 3736-3742.
[4.25] R. K. Pandey, R. Sathiyanarayanan, U. Kwon, V. Narayanan and K. V. R. M. Murali, “Role of point defects and HfO2/TiN interface stoichiometry on effective work function modulation in ultra-scaled complementary metal–oxide–semiconductor devices,” J. Appl. Phys., vol. 114, no. 3, pp. 034505-034505-7, Jul. 2013.
[4.26] M. Dai, Y. Wang, J. Shepard, J. Liu, M. Brodsky, S. Siddiqui, P. Ronsheim, D. P. Ioannou, C. Reddy, W. Henson, S. Krishnan, V. Narayanan, and M. P Chudzik, “Effect of plasma N2 and thermal NH3 nitridation in HfO2 for ultrathin equivalent oxide thickness,” J. Appl. Phys., vol. 113, p. 044103, Jan. 2013.
[4.27] A. Kechichian, P. Barboux, and M. Gros-Jean, ”Investigation on Oxygen Diffusion in a High-k Metal-Gate Stack for Advanced CMOS Technology by XPS,” Electrochemical Society Trans., vol. 58, no. 7, pp. 325-338, 2013.
[4.28] T. Yu, C. G. Jin, Y. Yang, L. J. Zhuge, X. M. Wu, and Z. F. Wu, “Effect of NH3 plasma treatment on the interfacial property between ultrathin HfO2 and strained Si0.65Ge0.35 substrate,” J. Appl. Phys., vol. 113, p. 044105, Jan. 2013.
[4.29] K. D. Bae, K. T. Lee, H. C. Sagong, M. H. Choe, H. W. Lee, S. E. Kim, K. S. Kim, J. K. Park, S. W. Pae, and J. W. Park, ” Effects of N-Rich TiN Capping Layer on Reliability in Gate-Last High-k/Metal Gate MOSFETs,” Electrochemical Society Trans., vol. 58, no. 7, pp. 3-7, 2013.
[4.30] B. Chen, R. Jha, H. Lazar, N. Biswas, J. Lee, B. Lee, L. Wielunski, E. Garfunkel, and V. Misra, “Influence of Oxygen Diffusion Through Capping Layers of Low Work Function Metal Gate Electrodes”, IEEE Electron Device Lett., vol. 27, no. 4, pp. 228-230, April 2006.
[4.31] Y.-L. Yang, W. Zhang, C.-Y. Cheng, Y.-P. Huang, P.-T. Chen, C.-W. Hsu, L.-K. Chin, C.-T. Lin, C.-H. Hsu, C.-M. Lai, and W.-K. Yeh, “Reliability Improvement of 28-nm High-k/Metal Gate-Last MOSFET Using Appropriate Oxygen Annealing”, IEEE Electron Device Lett., vol. 33, no. 8, pp. 1183-1185, Aug. 2012.
[4.32] H. F. Chiu, S. L. Wu, Y. S. Chang, S. J. Chang, J. F. Chen, S. C. Tsai, C. H. Hsu, C. M. Lai, C. W. Hsu, and O. Cheng, ” Impact of oxygen annealing on high-k gate stack defects characterized by random telegraph noise,” in Appl. Phys. Lett., vol. 101, no. 12, pp. 122105-122105-3, Sep. 2012.
[4.33] X. Garros, L. Brunet, M. Rafik, J. Coignus, G Reimbold, E. Vincent, A . Bravaix, and F. Boulanger, “PBTI mechanisms in La containing Hf-based oxides assessed by very Fast IV measurements”, in IEDM Tech. Dig., 2010, pp. 4.6.1-4.6.4.
[4.34] A. Kerber, S. A. Krishnan, and E. A. Cartier, “Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High-k Stacks”, IEEE Electron Device Lett., vol. 30, no. 12, pp. 1347-1349, Dec. 2009.
[4.35] J. Q. Yang, M. Masuduzzman, J. F. Kang, and M. A. Alam, “SILC-based reassignment of trapping and trap generation regimes of positive bias temperature instability”, in Proc. IEEE Int. Reliab. Phys. Symp., 2011, pp. 3A.3.1-3A.3.6.
[4.36] J. Yang, M. Masuduzzaman, K. Joshi, S. Mukhopadhyay, J. Kang, S. Mahapatra, and M. A. Alam, “Intrinsic correlation between PBTI and TDDB degradations in nMOS HK/MG dielectrics”, in Proc. IEEE Int. Reliab. Phys. Symp., 2012, pp. 5D.4.1-5D.4.7.
[4.37] A. T. Krishnan, C. Chancellor, S. Chakravarthi, P. E. Nicollian, V. Reddy, A. Varghese, R. B. Khamankar, S. Krishnan, “Material Dependence of Hydrogen Diffusion: Implications for NBTI Degradation,” in IEDM Tech. Dig., 2005, pp. 691-694.
[4.38] G. Krause, M. F. Beug, R. Ferretti, S. Prasad, K. R. Hofmann, “High-Field Degradation of Poly-Si Gate p-MOS and n-MOS Devices With Nitrided Oxides,” IEEE Trans. Device Mater. Rel., vol. 6, no. 3, pp. 473-478, 2006.
[4.39] C. L. Chen, Y. M. Lin. C. J. Wung. K. Wu, “A New Finding on NBTI Lifetime Model and an Investigation on NBTI Degradation Characteristic for 1.2nm Ultra Thin Oxide,” in Proc. Int. Rel. Phys. Symp., 2005, pp. 704-705.

Chapter 5

[5.1] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo”, Review on High-k Dielectrics Reliability Issues,” IEEE Trans. Device and Mater. Rel., vol. 5, no. 1, pp. 5-19, Mar. 2005.
[5.2] M. Aoulaiche, B. Kaczer, M. Cho, M. Houssa, R. Degraeve, T. Kauerauf, A. Akheyar, T. Schram, Ph. Rousse, H.E. Maes, T. Hoffmann, S. Biesemans and G. Groeseneken, “Positive and negative bias temperature instability in La2O3 and Al2O3 capped high-k MOSFETs”, in Proc. IEEE Int. Reliab. Phys. Symp., 2009, pp. 1014 – 1018.
[5.3] A. Kerber and E. A. Cartier, “Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks”, IEEE Trans. Device and Mater. Rel., vol. 9, no. 2, pp. 147-162, June 2009.
[5.4] K. Takeuchi, T. Nagumo and T. Hase, “Comprehensive SRAM Design Methodology for RTN Reliability”, in VLSI Symp. Tech. Dig., 2011, pp. 130-131.
[5.5] S. O. Toh, Y. Tsukamoto, Z. Guo, L. Jones, T. –J. K. Liu, and B. Nikoli´c, “Impact of Random Telegraph Signals on Vmin in 45nm SRAM”, in IEDM Tech. Dig., 2009, pp. 1-4.
[5.6] H. M. Kwon, I. S. Han, J. D. Bok, S. U. Park, Y. J. Jung, G. W. Lee, Y. S. Chung, J. H. Lee, C. Y. Kang, P. Kirsch, R. Jammy, and H. D. Lee, “Characterization of Random Telegraph Signal Noise of High-Performance p-MOSFETs With a High-k Dielectric/Metal Gate”, IEEE Electron Device Lett., vol. 32, no. 5, pp. 686-688, May 2011.
[5.7] N. Tega, H. Miki, F. Pagette, D. J. Frank, A. Ray, M. J. Rooks, W. Haensch, and K. Torii, “Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nm”, in VLSI Symp. Tech. Dig., 2009, pp. 50-51.
[5.8] K. Takeuchi, T. Nagumo, S. Yokogawa, K. Imai and Y. Hayashi, “Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude”, in VLSI Symp. Tech. Dig., 2009, pp. 54-55.
[5.9] J. P. Chiu, Y. T. Chung, Tahui Wang, Min-Cheng Chen, C. Y. Lu, and K. F. Yu, “A Comparative Study of NBTI and RTN Amplitude Distributions in High-k Gate Dielectric pMOSFETs” IEEE Electron Device Lett., vol. 33, no. 2, pp. 176-178, Feb. 2012.
[5.10] B. Kaczer, T. Grasser, Ph. J. Roussel, J. Franco, R. Degraeve, L.-A. Ragnarsson, E. Simoen, G. Groeseneken, and H. Reisinger, “Origin of NBTI variability in deeply scaled pFETs”, in Proc. IEEE Int. Reliab. Phys. Symp., 2010, pp. 26-32.
[5.11] Y. Tsukamoto, S. O. Toh, C. Shin, A. Mairena, T. –J. K. Liu, and B. Nikolić, “Analysis of the relationship between random telegraph signal and negative bias temperature instability”, in Proc. IEEE Int. Reliab. Phys. Symp., 2010, pp. 1117-1121.
[5.12] S. Pae, J. Maiz, C. Prasad, and B. Woolery, “Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies”, IEEE Trans. Device and Mater. Rel., vol. 8, no. 3, pp. 519-525, Mar. 2008.
[5.13] A. Asenov, A. R. Brown and B. Cheng, “Statistical aspects of NBTI/PBTI and impact on SRAM yield”, in Proc. Design Aut. Test Exh., 2011, pp. 1-6.
[5.14] B. Cheng, A. R. Brown, and A. Asenov, “Impact of NBTI/PBTI on SRAM Stability Degradation”, IEEE Electron Device Lett., vol. 32, no. 6, pp. 740-742, June 2011.
[5.15] S. E. Rauch, “Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations”, IEEE Trans. Device and Mater. Rel., vol. 7, no. 4, pp. 524-530, Mar. 2007.
[5.16] G. L. Rosa, W. L. Ng, S. Rauch, “Impact of NBTI Induced Statistical Variation to SRAM Cell Stability”, in Proc. IEEE Int. Reliab. Phys. Symp., 2006, pp. 274-282.
[5.17] T. Nagumo, K. Takeuchi, S. Yokogawa, K. Imai and Y. Hayashi, “New analysis methods for comprehensive understanding of Random Telegraph Noise”, in IEDM Tech. Dig., 2009, pp. 1-4.
[5.18] S. Realov and K. L. Shepard, “Random telegraph noise in 45-nm CMOS: Analysis using an on-chip test and measurement system”, in IEDM Tech. Dig., 2010, pp. 28.2.1-28.2.4.
[5.19] M. Toledano-Luque, B. Kaczer, J. Franco, Ph.J. Roussel, T. Grasser, T.Y. Hoffmann, and G. Groeseneken, “From mean values to distributions of BTI lifetime of deeply scaled FETs through atomistic understanding of the degradation”, in VLSI Symp. Tech. Dig., 2011, pp. 152-153.
[5.20] M. Cho, M. Aoulaiche, R. Degraeve, B. Kaczer, J. Franco, T. Kauerauf, P. Roussel, L. Å. Ragnarsson, J. Tseng, T. Y. Hoffmann and G. Groeseneken, “Positive and negative bias temperature instability on sub-nanometer eot high-K MOSFETs”, in Proc. IEEE Int. Reliab. Phys. Symp., 2010, pp. 1095-1098.
[5.21] K. Joshi, S. Mukhopadhyay, N. Goel and S. Mahapatra, “A consistent physical framework for N and P BTI in HKMG MOSFETs”, in Proc. IEEE Int. Reliab. Phys. Symp., 2012, pp. 5A.3.1-5A.3.10.
[5.22] S. Pae, A. Asho, J. Choi, T. Ghani, J. He, S. –h. Lee, K. Lemay, M. Liu, R. Lu, P. Packan, C. Parker, R. Purser, A. St. Amour, and B. Woolery, “Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology”, in Proc. IEEE Int. Reliab. Phys. Symp., 2010, pp. 287-292.

Chapter 6

[6.1] www.jedec.com, Standard qualification assessments are described in JESD22 and JESD78. In particular, HTOL is described in JESD22- A108D, “Temperature, Bias and Operating Life”, 2010.
[6.2] www.jedec.com, “Stress-test-driven qualification of integrated circuits”, JESD47H.01, 2011.
[6.3] Haggag, A., G. Anderson, S. Parihar, D. Burnett, G. Abeln, J. Higman, and M. Moosa. "Understanding SRAM hightemperature operating life NBTI: statistics and permanent vs recoverable damage." in Proc. Int. Rel. Phys. Symp., pp. 452-456, 2007.
[6.4] Kapre, R., K. Shakeri, H. Puchner, J. Tandigan, T. Nigam, K. Jang, M. V. R. Reddy, S. Lakshminarayanan, D. Sajoto, and M. Whately. "SRAM variability and supply voltage scaling challenges." in Proc. Int. Rel. Phys. Symp., pp. 23-28., 2007.
[6.5] A. Bansal, R. Rao, J. Kim, S. Zafar, J. H. Stathis and C. Chuang , "Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability," J. Micro. Rel., 2009, pp. 642-649.
[6.6] K. Kang, H. Kufluoglu, K. Roy and M.A. Alam, "Impact of Negative Bias Temperature Instability in Nano-Scale SRAM Array: Modeling and Analysis," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, 2007, pp. 1770-1781.
[6.7] Zhao Chuan Lee, Kim Ming Ho, Zhi Hui Kong, and Tony T. Kim, “NBTI/PBTI-Aware Wordline Voltage Control with No Boosted Supply for Stability Improvement of Half-Selected SRAM Cells,” SoC Design Conference, pp. 200-203., 2012.
[6.8] M. Alam et al., “A comprehensive model of PMOS NBTI degradation”, Microelectronics Reliability, vol. 45, no. 1, pp. 71- 81, Jan. 2005.
[6.9] S. Zafar et al., “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks,” JAP 2003.
[6.10] Rahman, A., M. Agostinelli, P. Bai, G. Curello, H. Deshpande, W. Hafez, C-H. Jan et al. "Reliability studies of a 32nm Systemon-Chip (SoC) platform technology with 2 nd generation highk/metal gate transistors." in Proc. Int. Rel. Phys. Symp., pp. 5D-3., 2011.
[6.11] Sato, M., N. Umezawa, J. Shimokawa, H. Arimura, S. Sugino, A. Tachibana, M. Nakamura et al. "Physical model of the PBTI and TDDB of la incorporated HfSiON gate dielectrics with preexisting and stress-induced defects." IEEE IEDM, pp. 1-4., 2008.
[6.12] S. Mukhopadhyay, K. Joshi, V. Chaudhary, N. Goel, S. De, R. K. Pandey, K. V. R. M. Murali and S. Mahapatra, “Trap Generation in IL and HK Layers During BTI/TDDB Stress in Scaled HKMG N and P MOSFETs” in Proc. Int. Rel. Phys. Symp., 2014
[6.13] J.C. Lin, A.S. Oates, H.C. Tseng, Y.P. Liao, T.H. Chung, K.C. Huang, P. Y. Tong, S.H. Yau, and Y.F. Wang, “Prediction and Control of NBTI – Induced SRAM Vccmin Drift,” in IEDM Tech. Dig., pp.345-348, 2006.
[6.14] A. T. Krishnan, V. Reddy, D. Aldrich, J. Raval, K. Christensen, J. Rosal, C. O’Brien, R. Khamankar, A. Marshall, W-K. Loh, R. McKee, S. Krishnan, ”SRAM Cell Static Noise Margin and VMIN Sensitivity to Transistor Degradation,” in IEDM Tech. Dig., pp.1-4, 2006.
[6.15] V. Huard, C. Parthasarathy, C. Guerin, T. Valentin, E. Pion, M. Mammasse, N. Planes, and L. Camus, “NBTI degradation: From transistors to SRAM arrays,” in Proc. IRPS, Phoenix, AZ, 2008, pp. 289– 300
[6.16] A. Bansala, R. Raoa, J.-J. Kima, S. Zafara, J. H. Stathisa, C.-T. Chuang, “Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability,” Journal Micro. Rel., 2009, pp. 642-649.
[6.17] Sangwoo Pae, Jose Maiz, Chetan Prasad, and Bruce Woolery, “Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies,” IEEE Trans. On Devie and Materials , vol. 8, no. 3, pp. 519-525, 2008.
[6.18] A. Asenov, A. R. Brown and B. Cheng, “Statistical aspects of NBTI/PBTI and impact on SRAM yield,” in Design, Automation and Test in Europe Conference and Exhibition, pp.1-6, 2011.