為能更有效利用構裝空間及提高接腳數，以滿足電子產品之高效能與輕便性需求，焊接點常以面積型態錫球陣列型式分佈在構裝體與印刷電路板間。由於組成構裝體與印刷電路板各元件間熱膨脹係數不同，因而在錫球處會導致顯著之熱應變及熱應力，繼而造成低週期熱疲勞破壞。
在探討面積型態構裝錫球的可靠度時，加速熱循環（accelerated temperature cycling）測試為JEDEC（Joint Electron Device Engineering Council）Test method A105-B規範中常使用的測試條件。由於大尺度面積型態構裝體結構材料組成複雜，除了實驗測試，有限單元法為一常使用的數值分析方法。唯為了求得錫球精確的熱應變/熱應力，建構有限單元分析模型常需要龐大的單元及節點數，尤以構裝中包含較大數目之錫球時更是如此。此外，錫球之塑性或潛變非線性材料性質，分析時亦不可忽略，此將進一步增加計算量，使得直接以有限單元法分析更為困難。
本論文旨在發展一簡單、有效的有限單元全域/局部分析法（global/local finite element approach），以探討在加速熱循環下之大尺度面積型態構裝錫球的熱應力/熱應變，進而評估其可靠度。在本論文發展之有限單元全域/局部分析法中，由於全域分析僅在找出可靠度最有問題之錫球及提供局部精細分析所需之變形量邊界條件，故在進行全域分析時，僅須利用恆溫潛變（Dwell Creep，DC）之錫球材料組成律（constitutive law）簡化模式，建構整個構裝體之全域有限單元分析精簡（compact）模型。而對可靠度潛在最有問題之錫球進行局部分析時，則須建構局部有限單元精細分析模型，並施予由全域分析所求得對應該顆錫球之變形量條件進行局部分析。此時錫球材料組成律須採用包含彈性（elastic）、塑性（plastic）及潛變 （creep）之完整特性，以精確計算錫球之熱應變/熱應力行為。
為檢驗本論文發展之有限單元全域/局部分析法之正確性及有效性，在應用例分析中，本論文首先以內含72顆錫球之大尺度單一晶片面積型態構裝為分析對象。所得結果並與採用三維有限單元分析精細模型及錫球材料組成律完整模式之傳統有限單元直接分析法（direct finite element approach）結果（benchmark）相比較。至於全域分析時，使用不同錫球材料組成律模式之影響，本論文亦予深入探討。結果顯示，應用本論文發展之有限單元全域/局部分析法，雖然於全域分析時採用最精簡之DC模式亦可準確的求得錫球的熱應變/熱應力，且其計算時間僅為直接分析法之五十分之一。本論文進一步預估錫球之疲勞壽命，與文獻中實驗值相較，亦獲得滿意之結果。本論文接著成功的將此有限單元全域/局部分析法推展應用於內含225及256顆錫球之單一晶片面積型態構裝及內含48顆錫球之堆疊式多晶片面積型態構裝中，以探討錫球之可靠度。為了驗證全域有限單元分析精簡模型，並以雲紋干涉實驗量測內含256顆錫球單一晶片面積型態構裝體之平面內位移加以比較，均獲得良好成果。
本論文最後結合反應曲面法（response surface method），有系統探討基材、封膠及銀膠之材料性質與晶片尺寸等設計參數對堆疊式多晶片面積型態構裝錫球可靠度的影響。並藉由F檢定法（F-test）、修正判定係數（adjusted coefficient of determination）及雲紋干涉實驗量測分別驗證所建立的反應曲面之準確性與適用性。透過本論文所建立堆疊式多晶片面積型態構裝之反應曲面，可快速且準確的評估各設計參數對錫球可靠度影響，以供構裝設計時之參考。

To improve the efficiency of packaging and increase the pin number for satisfying the higher performance and lightweight requirements of electronic products, solder joints, are often distributed in a ball-grid array area type between the package and printed circuit board (PCB). Due to the mismatch of thermal expansion coefficients among the components of electronic package and PCB, solder joints may endure significant thermal strain and stress, which will lead to a low cycle fatigue failures.
When investigating the reliability of solder joints in an area array typed package, accelerated temperature cycling (ATC) test is a typical test condition as indicated in the JEDEC (Joint Electron Device Engineering Council) Test method A105-B standard. Because a large-scale area array typed package consists of several complex components, the finite element method is adopted as a common numerical method in addition to experimental tests. To compute accurate thermal strain/stress of solder joints, the finite element model constructed usually needs huge number of elements and nodes, especially, when the package contains significant number of solder joints. In addition, the nonlinear material properties of plasticity and creep of solder joints need be taken into account in the analysis. This further increases the computational time and makes the analysis more difficult.
This study proposes a simple and effective global/local finite element approach for characterizing the thermal stress/strain of solder joints in an area array typed package under an ATC test, and eventually estimating their reliability. Since the global analysis is merely to identify the most suspicious solder joint for providing satisfactory displacements as external boundary conditions for the detailed local analysis, a simplified constitutive modeling strategy - Dwell Creep（DC）model is sufficient for establishing the compact global finite element model. However, a detailed local finite element model needs be constructed for analyzing the most suspicious solder joint subjected to the corresponding displacements computed from the global analysis. To evaluate accurate thermal strain/stress in the local analysis, a full constitutive modeling strategy comprising the elastic, plastic and creep responses is performed.
To demonstrate the accuracy and effectiveness of the proposed approach, this study first adopts an area array typed package containing 72 solder joints as a test vehicle in case studies. The accuracy of the solutions computed from the proposed approach is demonstrated by comparing with a benchmark, which employs a conventional 3-D direct finite element analysis approach and fine-meshed finite element model and the full constitutive modeling strategy. In addition, the effects of constitutive modeling strategies in the global analysis are also extensively explored. The results show that the proposed approach can yield a satisfactorily accurate solution even it is associated with the most simplified constitutive modeling strategy, DC model. The computational time of the proposed approach is about fiftieth of the direct finite element approach. Furthermore, this study also estimates the fatigue life of solder joint. As compared with existing experimental fatigue life data, the proposed approach yields satisfactory results. The proposed approach then successfully applies to the investigation of solder joints reliability of the two single-chip area array typed packages that contain 225 and 256 solder joints and a stacked multichip area array typed package containing 48 solder joints. This study also validates the compact global finite element model for the area array typed package containing 256 solder joints by comparing with the moiré interferometric measurement of the in-plane displacement field.
Finally, the proposed approach combining with the response surface method is adopted to estimate the influence of design parameters on the reliability of solder joints in a stacked multichip area array typed package. These design parameters include material properties of the substrate, the molding compound and silver adhesive and the size of chips. By the F-test, the adjusted coefficient of determination and the moiré interferometric measurement, the accuracy and applicability of these response surfaces are demonstrated. Based on these response surfaces, the influence on the solder joint reliability can be quickly and accurately estimated. These results would be quite helpful in the package design.

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