研究生: |
徐敏軒 Hsu, Min Hsuan |
---|---|
論文名稱: |
球閘陣列型態封裝之修訂加速因子研究 Research on Modified Acceleration Factor for BGA Type Package |
指導教授: |
江國寧
Chiang, Kuo Ning |
口試委員: |
鄭仙志
李昌駿 |
學位類別: |
碩士 Master |
系所名稱: |
工學院 - 動力機械工程學系 Department of Power Mechanical Engineering |
論文出版年: | 2016 |
畢業學年度: | 104 |
語文別: | 中文 |
論文頁數: | 106 |
中文關鍵詞: | 球閘陣列型態封裝 、加速因子 、最高溫度 、潛變 、Garofalo Hyperbolic Sine模型 、Coffin-Manson應變法 、Darveax能量密度法 |
外文關鍵詞: | Ball Grid Array, Acceleration Factor, Maximum temperature, Creep, Garofalo Hyperbolic Sine Model, Coffin-Manson strain based model, Darveax energy based model |
相關次數: | 點閱:2 下載:0 |
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隨著消費性電子產品及手持式裝置的興起,電子封裝技術持續朝向輕量化、微小化、高密度以及高功率發展,如球閘陣列封裝(Ball Grid Array, BGA)逐漸取代傳統四邊接腳型態封裝(Quad Flat Package, QFP),其優勢是將I/O的分佈形式以面積型態取代四邊接腳型態,以達到高密度I/O之需求。近年來擁有較小封裝尺寸的晶圓級晶片尺寸封裝(Wafer Level Chip Size Packaging, WLCSP)逐漸受到大家的關注,WLCSP和BGA一樣是使用錫球來連接PCB板,但不同之處為WLCSP是整片晶圓生產完成後,直接在晶圓上進行封裝測試,完成後才將其切割成單顆IC,整個過程不需經過打線和填入底膠(Underfill),因此封裝後的晶片尺寸大小等同於原本的晶片。由於未填入底膠的關係,WLCSP往往在結構設計時會加入緩衝層(Buffer Layer)之設計,以避免晶片與基板因熱膨脹係數不匹配使得錫球產生過大的應變進而過早發生破壞。
一般針對球閘陣列型態封裝的可靠度測試會使用熱循環實驗(Thermal cycling test),將測試載具置入比實際使用情形更嚴苛的環境中,加速試件破壞,以降低可靠度測試時間,再搭配可信賴之加速因子(Acceleration Factor, AF)使其迅速反推原始負載強度下之壽命,以達到縮短產品上市時程之目的,也因此加速因子必須具有一定的準確度。但球閘陣列型態封裝的可靠度測試實驗通常仍需耗費大量成本及數個月的時間方能完成,因此若能使用有限元素模擬之數值方法,模擬封裝結構受到與實驗相同之溫度負載,並搭配少量的實驗與模擬結果做驗證,必定能大幅降低測試的成本及時間。
加速因子起初是由Norris和Landzberg提出,由Norris-Landzberg加速因子公式中可以得知加速因子主要由三個部分所組成,分別為高低溫差、頻率以及最高溫度項。本研究的重點在修正N-L加速因子公式,使得修正後的加速因子公式能更準確的預估不同溫度負載條件下封裝結構的疲勞壽命。當探討改變最高溫度對封裝結構可靠度影響時,需固定頻率項及高低溫差項,以便將最高溫度效應獨立出來討論,同樣地當要探討高低溫差項或頻率項時,需固定另外兩項。因此本研究在探討最高溫度時,溫度負載採用JEDEC 標準測試規範中的0°C到125°C為基準,在固定頻率和高低溫差的情況下增加其他組溫度負載進行模擬分析。探討高低溫差時,溫度負載採用JEDEC 標準測試規範中的-40°C到125°C為基準,在固定其他兩項的前提下進行分析。頻率項的部分將其分為升降溫速率和持溫時間來討論。由於N-L加速因子公式適用於球閘陣列型態封裝,因此有限元素模型的部分採用一樣是使用錫球作為訊號連接的WLCSP結構。
上述溫度負載之溫度在大部分的時間下都超過錫球熔點絕對溫度(K)的三分之一,這使得錫球的潛變現象變得更加明顯,因此在熱循環過程中會產生額外的潛變應變,潛變應變的累積會使得錫球提早破壞因此必須納入考量。本研究採用Garofalo Hyperbolic Sine Model來模擬錫銀焊料合金錫球之潛變行為,並且採用動態硬化法則模擬錫球受加載和卸載後的塑性行為。
本研究中使用了兩種不同之壽命預估模型,分別為Coffin-Manson應變法及Darveax能量密度法。然經由模擬結果顯示在改變最高溫度的情況下,潛變應變能密度增量並不明顯,將此結果帶入Darveaux能量密度法後無法得到與實驗結果相同之趨勢,但在潛變應變方面將其模擬結果帶入Coffin-Manson應變模型後,可以得到與實驗相同之壽命趨勢,因此本研究利用Coffin-Manson應變法預估出的疲勞壽命進行加速因子公式中之最高溫度項的修正。 最後將三個項都修正過的加速因子公式與任意溫度之實驗壽命數進行驗證,發現修正過之加速因子公式預估出的壽命比起原始的N-L加速因子公式所預估出的壽命要更接近實驗壽命數。
With the rise of consumer electronics and handheld devices, electronic packaging becomes lightweight, smaller, high I/O and high-power. For example, the use of solder balls of ball grid array (BGA) package gradually replaces Quad Flat Package (QFP) in order to increase the I/O counts. In recent years, Wafer Level Chip Size Packaging (WLCSP) catches everyone's attention due to its small size. Both WLCSP and BGA use solder balls to connect die and the substrate, but the difference is that WLCSP is packaged directly on a wafer and it doesn’t need the wire bonding and underfill but buffer layer. The purpose of buffer layer is to increase the mean time to failure of the solder ball which is due to the CTE mismatch between the chip and the substrate.
The thermal cycling test is a standard method which is currently used to characterize the reliability performance of electronic packaging. The test vehicles are placed in a condition which is harsher than the actual usage condition in order to reduce the testing and development time. Then use the acceleration factor to predict the fatigue life which is under original test condition, so acceleration factor must be accurate. Using the finite element simulation with a few experiments can reduce the testing time again.
The original acceleration factor model was proposed by Norris and Landzberg which includes temperature range, temperature-cycling frequency and the maximum temperature. In this research, the three terms maximum temperature, temperature range and frequency will be modified, and compared with experimental results. To investigate the maximum temperature term, thermal cycling test condition refers to JEDEC standard in which the temperature range is between 0°C to 125°C while the others are -10°C to 115°C and -20°C to 105°C. To investigate temperature range term, thermal cycling test condition refers to JEDEC standard which the temperature range is between -40°C to 125°C and others are -20°C to 105°C and 0°C to 85°C. The frequency term will be discussed by dividing into ramp rate and dwell time. Because Norris-Landzberg acceleration factor is only feasible for BGA type package, a simulation model of wafer level chip scaling package is constructed in this research.
Because the temperature under accelerated thermal cycling test always exceeds one third of the melting point (in Kelvin) of the solders, the creep effect becomes ineligible and needs to be considered. In this study, Garofalo Hyperbolic Sine Model is used to simulate the creep behavior of the lead-free SnAg solder alloy and kinematic hardening model is used to simulate the plasticity behavior.
In this study, two life prediction models are selected to investigate the reliability of WLCSP. One is Coffin-Manson strain based model and another one is Darveaux energy based model. The simulation results show that the increment of creep strain energy density has changed insignificantly, so the fatigue life does not coincide with the experimental results when Darveaux model is applied. However, the increment of creep strain increases with the increase of maximum temperature which is same as the experimental result. Therefore, Coffin-Manson strain based model is applied to modify the maximum temperature term in the original acceleration factor model. Finally, compare our complete modified acceleration factor model with the experimental results under arbitrary temperature, and it shows that our acceleration factor model is more accurate than the original N-L acceleration factor model.
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