This paper presents a hardware-friendly shuffled message-passing decoding
(MPD) method that can be used to design efficient multiple-standard lowdensity
parity-check (LDPC) decoders. In this shuffled MPD, two compensation
factors, rather than one factor, are dynamically used in the offset Min-Sum
algorithm such that the number of quantization bits can be reduced without
degradation in error performance. Using the proposed shuffled MPD, the storage
requirements can be further reduced since artificial minimum values, which
do not need to be stored in memory, are used in the check-node operation. In
the shuffled MPD, variable nodes are divided into several groups and decoding
operations are executed group by group such that the critical path can be
shortened in order to realize a high-throughput decoder. We propose an algorithm
to partition these groups such that the hardware cost can be minimized
and the up-to-date decoding messages can be utilized. Using the proposed
techniques, a multi-standard decoder that supports LDPC codes specified in
the ITU G.hn, IEEE 802.11n, and IEEE 802.16e standards was designed and
implemented using a 90-nm CMOS process. This decoder supports 133 codes,
occupies an area of 5.529 mm2, and achieves an information throughput of
1.956 Gbps at a clock frequency of 400 MHz based on post-layout results.

在這篇論文中，我們提出了一種硬體友好並適用縱向混合解碼演算法
（Shuffled MPD）和高效率的解碼器架構建構在多重通訊標準下的低密度
奇偶校驗碼（LDPC）。在Shuffled MPD中，兩個補償因子取代一個補償
因子動態地用於補償演算法，這樣的量化比特數可以減少且不退化更正錯
誤能力的表現。改良Shuffled MPD的演算法，並提出人工的第三小值不須
儲存在記憶體中用於檢查節點運算，在低碼率下，如此可大大減少儲存的
空間。在Shuffled MPD，可將位元節點分成若干群組，解碼依序運算若干
群組，硬體的主要路徑（Critical Path）可以被縮短，以實現高吞吐量的
解碼器。我們提出使用搜尋演算法來分割這些群組，可讓記憶體分配的面
積最小化，並能有效率地降低效能的衰減。使用上述我們提出的技術，一
個多標準ITU G.hn，IEEE 802.11n和IEEE 802.16e的LDPC解碼器設計並使
用90-nm CMOS製程。這個解碼器可以支援3種不同通訊標準共133種模態，
在post-layout下的結果，占了面積5.529mm2，且在頻率為400MHz之下最快
可達到資料吞吐量1.956 Gbps。

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