採用直接數位除頻電路之分數型頻率合成器｜國立清華大學博碩士論文庫

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研究生：	陳欣煒 Hsin-Wei Chen
論文名稱：	採用直接數位除頻電路之分數型頻率合成器 A Fractional-N Frequency Synthesizer with Direct Synthesis Divider
指導教授：	黃柏鈞 Po-Chiun Huang
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	119
中文關鍵詞：	頻率合成器、分數型架構、直接數位除頻電路、相位雜訊、相位內插、分數誤差補償
外文關鍵詞：	Frequency Synthesizer, Fractional-N architecture, Direct Synthesis Divider, Phase Noise, Phase Interpolation, Fractional Error Compensation
相關次數：	點閱：4 下載：0
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頻率合成器是無線通訊系統中一個重要的構成單元，負責執行高頻載波與基頻信號之間的轉換。其設計優劣決定了信號轉換的品質與傳輸系統的性能。在一個射頻無線傳輸系統中，頻率合成器大多以鎖相迴路的型式來實現。在設計上，以和差調變分數型鎖相迴路架構為目前的主流。此種架構，結合了多模數除頻器(Multi-modulus divider)與和差調變器(Σ-Δ modulator)，來實現一個分數型除頻電路。然而，此種架構最大的限制在於分數型誤差(Fractional error)的產生。此誤差的存在，對於鎖相迴路頻寬的延伸有著不利的影響。

本論文研究之方向，著重於分數型誤差的產生與消除。為突破前述架構在迴路頻寬上的限制，我們提出一個利用直接數位合成方式來實現之分數型除頻電路。此除頻電路，藉由其相位內差的機制，能實現一個接近於真實分數除頻器的行為，並能有效的降低分數型誤差的產生，來達到誤差補償的效果。透過線性系統分析與行為的模擬，我們能初步確立此架構之可行性，並得出分數補償的效果。

在電路上，本論文實現了一個輸出頻率在4.63GHz到5.56GHz分數型頻率合成器原型，主要採用TSMC 0.18μm CMOS製程來進行設計及佈局。本頻率合成器採用一10MHz之參考時脈頻率，電路之頻率調整解析度可達18.6KHz。並且，可在16μsec之時間內，完成頻率鎖定的動作。相位雜訊的強度上，於頻寬範圍內可達-80dBc/Hz。本電路包含I/O pad之晶片面積共計2.1mm2 (若不含I/O PAD 則為1.15mm2)。在電路正常動作下，功率消耗約為52.8mW。晶片實際量測之結果顯示其降低分數誤差的效果，與行為模擬所得之結果大致相符。

在量測的過程中，我們也發現了一些先天上的限制，這些限制影響了本架構的應用層面。針對這些問題，我們也提出一些看法與可改進的方向以助於後續相關的研究。

Frequency synthesizer is in charge of generating a high quality signal source for passband transceiver up- and down-conversions. For a high resolution synthesizer design, the Σ-Δ fractional-N structure is widely adopted. Combining a Σ-Δ modulator with the multi-modulus divider, a frequency divider is capable of emulating fractional multiple of reference frequency in the PLL output. However, the fractional error, which inevitably comes from the timing quantization, dominates the PLL output noise and limits the loop bandwidth.

In this thesis, efforts are dedicated to the reduction of fractional error for PLL bandwidth extension. A new fractional division technique is proposed and implemented in TSMC 0.18μm CMOS process. By applying the direct synthesis circuit in PLL, a nearly true fractional divider can be achieved. The fractional error is compensated via phase interpolation and the error reduction can be conceptually proven by behavioral simulation.

The idea is validated in silicon measurement. In this work, a fractional-N frequency synthesizer is realized. Measurement results show that the synthesizer can generate frequency signals ranging from 4.63GHz to 5.56GHz with 18.6KHz output frequency resolution and 16μsec settling time. The in-band phase noise can achieve -80dBc/Hz. Chip area of this synthesizer is 2.1mm2, including I/O pad. This circuit consumes a power of 52.8mW under normal operation.

During the design and measurement, some practical issues about this architecture are also discovered. The suitable applications are therefore restricted. Toward those issues, some discussions are addressed for the future improvement.

   Motivation                                                    1
1.    Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.    Thesis Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

   Fundamentals of Frequency Synthesizer                            5
1.    Direct Frequency Synthesis .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.    Direct Digital Frequency Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.    Indirect Frequency Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.    Integer-N PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.    Fractional-N PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

   Quantization Noise and Techniques for Noise Compensation        12
1.    Operation of Σ − Δ Fractional-N Architecture . . . . . . . . . . . . . . .. . . 13
2.    Quantization Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.    Error Caused by Fractional-N Architecture . . . . . . . . . . . . . . . . . . . . . . 17
2.2.    Quantification of Timing Quantization . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.    Fractional Error Compensation Techniques . . . . . . . . . . . . . . . . . . . . . . . 21
3.1.    Current DAC Fractional Compensation . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.    Phase Interpolated Fractional Compensation . . . . . . . . . . . . . . . . . . . . . 22
4.    Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

   Fractional-N Frequency Synthesizer with Direct Synthesis Divider   27
1.    Block Diagram of Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.1.    Concept of Phase Interpolation Using DSD . . . . . . . . . . . . . . . . . . . . . . 29
2.    Direct Synthesis Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.1.    Non-ideality in DSD Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.    Spectrum of DSD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3.    A Spur-reduced DSD Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.    Behavior Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1.    Time Domain PLL Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.2.    Phase Domain PLL Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.    Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

   Circuit Level Implementation                                    67
1.    Voltage Control Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.1.    VCO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.2.    Design Issues about VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
1.3.    Physical Design and Circuit Simulations . . . . . . . . . . . . . . . . . . . . . . . . 86
2.    Prescalar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.1.    Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.2.    Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.    Direct Synthesis Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.1.    Digital Synthesis Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.2.    Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.    Phase Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.    Miscellaneous Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

   Measurement                                               102
1.    Prototype of Fractional Synthesizer with DSD . . . . . . . . . . . . . . . . . . . . 103
1.1.    Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
2.    Measurement Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2.1.    VCO and High Speed Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.2.    Direct Synthesis Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.3.    Closed-loop Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

   Conclusion and Future Work                                   115
1.    Limitation of DSDPLL Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
2.    Possible Solution for Future Performance Improvement . . . . . . . . . . . . 117

                                

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