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研究生: 楊宏文
Hung-wen Yang
論文名稱: MB-OFDM UWB 基頻內部接收機晶片整合設計與多接收天線通道縮短技術
Integration of MB-OFDM UWB Baseband Inner Receiver Design and Channel Shortening Technology with Multiple Receive Antennas
指導教授: 吳仁銘
Jen-ming Wu
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 通訊工程研究所
Communications Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 英文
論文頁數: 74
中文關鍵詞: 正交分頻多工通道縮短超寬頻系統
外文關鍵詞: OFDM, channel shortening, UWB
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  • 超寬頻系統(UWB) 是目前最受到矚目的寬頻無線存取技術之一,它的主要優勢在於能夠在短距離之內高速傳輸資料,它的傳送速度從53.3Mb/s 到 480Mb/s。它也是目前相當有潛力能成為未來個人區域網路(PAN) 的通用系統,能被運用在資料、影像以及聲音的傳輸上。多頻帶正交分頻多工超寬頻系統(MB-OFDM UWB)有別於一般單一載波通訊系統,使用正交分頻技術(Orthogonal frequency-division multiplexing),擁有良好的頻寬使用率、符元間干擾較小以及可利用快速傅立葉轉換來實現多重載波調變等優點,並且利用多頻帶(Multi-Band)的特性增加多樣性(Diversity)。
    在目前多頻帶正交分頻多工超寬頻系統標準下,使用128點快速傅立葉轉換,資料傳輸速度最快可達到480Mbs,這使得多頻帶正交分頻多工超寬頻系統成為目前當紅的無線通訊存取技術之ㄧ。
    在本論文中,我們針對多路徑效應(Multipath Effect) 嚴重的通道,提出了利用通道縮短技術(Channel Shortening Technique)與多接收天線(Multiple Receive Antennas)的架構來提升系統可靠性。同時,我們也提出模擬結果來加以驗證。我們並且實做MB-OFDM UWB 的內部接收機電路,其中包括同步電路、快速傅立葉轉換電路以及通道補償電路。
    在第一章,我們首先簡介MB-OFDM UWB系統,並且在第二章簡要地講述OFDM系統的特性以及MB-OFDM UWB系統標準。在第三章,我們介紹運用於OFDM數位接收機的理論背景,包括時間同步、快速傅立葉轉換以及頻道估測與補償的演算法,多接收天線通道縮短架構也在第三章提到。在第四章,我們完整地講解硬體架構以及實做時的一些考量,晶片設計以及系統模擬會在第五章呈現。


    UWB system is one of the most popular broadband wireless access technologies. Its main advantage is the capability of transmitting high rate data in a short distance. It is also a potential candidate for future wireless personal area network, and can be widly adopted in transmission of data, video and voice.

    In this thesis, we implement a baseband inner receiver for MB-OFDM UWB, including synchronization, Fast Fourier Transform, and channel equalization circuits. We also propose a channel shortening with receiver diversity scheme to deal with multipath environment. Detail simulations and derivations are also given in this thesis.

    Contents Contents…………………………………………………………………………...i List of Figures………...………………………………………………………….v List of Tables…………………………………………………………………viii Abstract…………………………………………………………………………...ix Chapter 1 Introduction………………………………………………………………………..1 1.1 Overview of MB-OFDM UWB……..………………………......2 1.2 Features of MB-OFDM UWB………………………………....2 Chapter 2 OFDM and Specification of MB-OFDM UWB………………...........3 2.1 OFDM Basics…………………………………………………………....3 2.1.1 OFDM Introduction…………………………...….………………....3 2.1.2 OFDM Concepts………………………....………………………....3 2.2 Specification of MB-OFDM UWB….…………………....................8 2.2.1 Introduction………………………....………...….……………….....8 2.2.2 Mathematical Framework…………….……...….………………....9 2.2.3 UWB Physical Layer Parameters………..........….………………...11 2.2.4 Frame-related parameters........………………….………………...12 2.2.5 PLCP Preamble........…………………...……….………………...12 2.2.6 Constellation Mapping........…………………….………………...16 2.2.7 Inverse Fast Fourier Transform........…………....………………...19 2.2.8 Zero-Padded Suffix (ZPS)........……………..........………………...20 Chapter 3 Fundamental Algorithm of OFDM Receiver…………………...…..21 3.1 Packet Detection………………………………..………………………21 3.1.1 Concept of Packet Detection……………………………………….21 3.1.2 Delay and Correlate Method……………………………………….22 3.2 Carrier Frequency Offset…………….……………………………..23 3.2.1 Concept of Carrier Frequency Offset………………………………23 3.2.2 Carrier Frequency Offset Estimation………………………………24 3.3 Symbol Timing Estimation…………….…………………………24 3.3.1 Concept of Symbol Timing………………………………….……..24 3.3.2 Symbol Timing Algorithm…………………………………………25 3.4 Fast Fourier Transform…...……………………………………26 3.4.1 Concept of FFT………….…………………………………………26 3.4.2 Decimation in Time FFT…………………………………………...27 3.4.3 Decimation in Frequency FFT…………………………………......28 3.5 Channel Estimation…..…...…………………….……………29 3.5.1 Concept of Channel Estimation…………………………………….29 3.5.2 Frequency Domain Approach…………………………………….29 3.6 Channel Models…………………………………………..……31 3.7 Impulse Response Shortening with Receive Diversity...………33 3.7.1 Concepts of Impulse Response Shortening…………………...……33 3.7.2 Proposed Method…………………………………………………...34 3.7.3 Simulation and Discussion……………………………………...….39 3.7.4 Summary...………………………………………………………….45 Chapter 4 Implementations of MB-OFDM UWB Receiver…………………...46 4.1 System Block Diagram…………………….…………………........46 4.1.1 Inner Receiver Data Flow Diagram………………………….……..47 4.1.2 Binary Number Representations…………………………………48 4.2 Architecture of Synchronization…………………….……….......49 4.3 Architecture of FFT………………………………………….......52 4.3.1 FFT Architecture…………………..………….……………………52 4.3.2 ZP Removal Buffer……………...………………………………….53 4.4 Architecture of Channel Estimator and Compensator……….......55 4.4.1 Estimator Architecture……………..………….……………………57 4.4.2 Compensator Architecture………………………………………….59 4.4.3 SRAM Controller…………………………………………………60 Chapter 5 Simulation Results and Chip Design…………………….……………...62 5.1 Simulation Results…………………………………...…………62 5.1.1 System Simulations……………..………….……………………62 5.1.2 RTL Simulations……………..………….………………………….63 5.1.3 Gate Level Simulations……..……..………….……………………65 5.2 Chip Design……..…………………………………...…………65 5.2.1 Overall Architecture……………..………….……………………65 5.2.2 Interface Signals……………………………………………………66 5.2.3 Chip Specification List…..…………………………………………67 5.2.4 Chip Layout View…..……………………………………………68 Chapter 6 Conclusion and Future Work………………………………………………72 Biblography……………………………………………………………………73

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