浸鍍錫技術最早被使用於防止銅質水管生鏽造成飲用水中銅含量過高的抗蝕層。之後逐漸被應用於電路板製造的領域。由於鍍純錫於銅線路上被發現會有錫鬚生長並因此造成電子元件短路, 因此純錫鍍層於電路板製程上的應用受到極大的限制, 浸鍍錫的鍍層亦是純錫鍍層的一種, 故其發展也同時受到限制。然而最近幾年來由於受到無鉛化的影響, 各種無鉛化的技術都逐漸受到重視, 包括浸鍍錫的技術。此外, 由於持續的研發, 浸鍍錫的藥水與製程技術都已有長足的進步而且有許多之前不為人知的優點被發現, 因此浸鍍錫的技術又重新受到電子業的重視。目前浸鍍錫的技術被電路板製造業使用於電路板線路的最終化處理, 且被列為新一代無鉛化金屬最終處理的選擇之一。然而, 浸鍍錫技術可以應用的範疇不只是表面最終處理而已, 還可以應用於許多電路板製造製程。這些部分是十分重要卻又缺乏理論基礎的。
本論文旨在探討浸鍍錫鍍層的基本特性與使用於電路板製造的各項應用: 於本論文中, 首先, 先針對應用於電路板最終化處理的浸鍍錫鍍層特性包括鍍層狀態、介金屬層的生成以及錫鬚的成長等等進行探討。吾人發現浸鍍錫鍍層的發展為, 先生成介金屬層再生成純錫層。當鍍層生成後, 由於原子擴散的關係銅會持續由基材銅擴散到鍍層中與錫反應生成銅/錫介金屬層。由於擴散是持續的因此介金屬層會隨時間持續生長直到純錫完全消耗。 由於介金屬層的比重與銅以及錫的比重都不相同, 因此介金屬層的生長會造成鍍層內體積的變化並因此造成鍍層內空洞以及應力的形成, 當應力累積到一定的程度以後會促成錫鬚的生長, 藉此來釋放應力。
錫鬚為單晶結構其生長也會消耗純錫層, 因此當純錫層消耗完, 錫鬚的生長也會停止。錫鬚的生成會造成短路等會影響電路板產品信賴度的問題, 因此吾人於本論文中亦針對抑制錫鬚的方法進行研究。 由於應力是造成錫鬚生長的必要條件之一, 而原子的擴散又是造成應力生成的根本因子, 因此我們發展出一種利用有機阻隔層來降低原子擴散速度的方法來抑制錫鬚的生長, 我們發現利用Nafion 來當阻隔層可以抑制錫鬚的生長, 雖然無法完全解決錫鬚的問題但是可以延長錫鬚生長所需要的時間。進而提升產品穩定度。
浸鍍錫技術除了可應用於金屬最終化之外, 還可以應用於電路板線路製作流程, 作為蝕刻阻劑; 以及壓合製程, 作為壓合介質以增加壓合強度。在當蝕刻阻劑的部份, 我們發現厚度僅約1.5µm的鍍層可於無噴壓的狀態下承受約有60µm/min蝕刻能力的銅蝕刻液30分鐘以上的攻擊, 並可以於1.5kg/cm2 的噴壓下證實其抗蝕刻能力, 甚至於2.5kg/cm2 的噴壓下, 可以製作出接近完美的長方體線路。
應用於壓合製程時發現, 鍍上一層浸鍍錫可以提升銅箔的表面微粗糙度, 並因此可以增加銅箔與基板間的壓合強度; 當此浸鍍錫鍍層有經過Nafion預鍍處理時其表面微粗糙度會進一步提升, 可以得到更好的壓合強度。
傳統提升表面粗糙是使用化學蝕刻的方法, 然而要得到一個夠粗糙的面往往要蝕刻掉3~12 µm的銅, 吾人發現浸鍍錫處理過的銅面受到浸鍍錫置換反應的影響會造成一個均勻且具有微粗糙結構的表面, 可以應用於許多製程, 吾人將此粗糙面拿來壓合, 發現有很好的效果, 足可應付壓合所需。

Immersion tin coating, which is used as a lead-free surface finish, is deposited on the surface of copper circuitries on circuit boards by a replacement reaction. The characteristics of immersion tin coatings and the formation of tin whiskers and the intermetallic compound (IMC) are described. A Cu6Sn5 phase forms at the beginning of the immersion plating process and expands until all of the tin has been transformed into a copper-tin alloy. The IMC layer becomes thicker and the volume of the pure tin layer decreases during storage.
The densities of tin, copper and IMCs are different. Therefore, the IMCs formation reaction can cause volume changes and voids were observed in the coatings. Moreover, the tin involved in the formation of whiskers must originate from the tin layer of the immersion tin coating. Therefore, the formation of tin whiskers stops when all of the tin has been expended. Moreover, relatively larger whiskers grow on thicker coating layers, which contain more tin.
Atomic diffusion at room temperature and stress formation are necessary conditions for spontaneous growth of tin whiskers. Therefore, a barrier film deposited on the copper / tin interface can reduce the formation of tin whiskers. In this study, organic films (Nafion and PTFE) were coated on the surface of copper substrates as a barrier layer before the immersion plating, and decreased the rate of atomic diffusion. This had the effect of limiting the amount of copper in the immersion tin coating, and the irregular formation of IMCs was inhibited. In turn, the stresses caused by IMCs, and hence the formation of tin whiskers, were reduced.
Immersion tin is used as etching resist and is selectively applied to the metal layer to leave areas of coated and uncoated metal followed by etching the metal not coated with the resist. Porous coating structure should be avoided due to etching solution can attack copper through these pores. Moreover, Nafion modified immersion tin coatings were used to improve its performance. A modified pattern plating process is disclosed for manufacturing a circuit board having a metal layer in which a portion of the metal layer is removed by etching.
In the manufacture of PCB's, a metal conductive foil such as copper is bonded to the circuit board. The immersion tin coatings could be used in the manufacture of circuit boards as bonding medium. A method of using immersion tin coatings as bonding medium for improving the adhesion of PCBs in a multilayer board and a new process to make rough copper surfaces were described in this chapter. Coating a tin layer in the copper surface can improve its adhesion to the circuit board. Moreover, stripping the tin coating can make a rough copper surface with higher peel strengths.

Chapter 1
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2. A. M. Soutar, P. T. McGrath, U.S. Patent No.6,860,925(2005).
3. Y. Mikado, Y. Hiramatsu and H. En, U.S. Patent No.6,242,079(2001).
4. J. L. Cordani, U.S. Patent No.4,775,444(1988).
5. S. Louis J., T. James and K. Thomas, U.S. Patent No.5,593,499(1997).
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8. M. Sleppin, Plating and Surface finishing, 75 (1998) 42.
9. J. J. Sundelin, S.T. Nurmi and T.K. Lepisto, Journal of Electronic materials, 35 1600(2006).
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12. E. W. Kinkelaar, H. G. Pekar, U.S. Patent No.4,618,513(1986).
13. B. D. Dunn, Circuit World 2(1976)32.
14. B. D. Dunn, Metals and Materials, 34(1975)32.
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17. The Plating Processes Subcommitte of the Fabrication Process Committee of IPC,“IPC-4553 Specification for Immersion Silver Plating for Printed Circuit Boards”., Illinois, IPC, (2005).
18. E. Huttunen-Saarivirta, Surf. Tech., 160, (2002)288.
19. S. Lamprecht, Circuit World, 31, 2,15(2005).
20. M. K. Huang, C. Lee and P. L. Wu, Soldering SMT, 17, 3(2005).
21. S. T. Nurmi, J. J. Sundelin, and E. O. Ristolainen, Soldering SMT, 17, 13(2005).
22. E. Huttunen-Saarivirta, T. Tiainen, T. Lepisto, Mater. Sci. Eng., A336, 52(2002).
23. E. Huttunen-Saarivirta, Surf. Tech., 165, 101(2003).
24. K. N. Tu, Acta Metall., 21, 347(1973).
25. J. W. Mayer, J.M. Poate, and K.N. Tu, Science 190, 228(1975).
26. K. N. Tu, R. D. Thompson, Acta Metall., 30, 947(1982).
27. T. Fang, M. Osterman, M. Pecht, Microelectron. Reliab., 46, 846(2006).
28. NASA Goddard Tin Whisker Website, http://nepp.nasa.gov/whisker/
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Chapter 2
1. C. F. Coombs, Jr.,“Printed Circuits Handbook”, 4th ed., New York, McGraw-Hill, (1995).
2. E. Huttunen-Saarivirta, T. Tiainen, T. Lepisto, Mater. Sci. Eng., A336, 52(2002).
3. E. Huttunen-Saarivirta, Surf. Tech., 160, 288(2002).
4. E. Huttunen-Saarivirta, Surf. Tech., 165, 101(2003).
5. K. N. Tu, Acta Metall., 21, 347(1973).
6. J. W. Mayer, J.M. Poate, and K.N. Tu, Science 190, 228(1975).
7. K. N. Tu, R. D. Thompson, Acta Metall., 30, 947(1982).
8. T. Fang, M. Osterman, M. Pecht, Microelectron. Reliab., 46, 846(2006).
9. W. J. Choi, T. Y. Lee, K. N. Tu, N. Tamura, R. S. Celestre, A. A. MacDowell, Y.Y. Bong, and Luu Nguyen, Acta Mater., 51, 6253(2003).
10. K. S. Kim, C. H. Yu, J. M. Yang, Thin Solid Films, 504, 350(2006).
11. B. Z. Lee, and D. N. Lee, Acta Mater., 46, 3601(1998).
12. R. Zeng, Z. Pang, H. Zhu, J. Electroanal. Chem., 490, 102(2000).
13. L. Hwa-Teng, C. Ming-Hung, Mater. Sci. Eng., A333, 24(2002).
14. The Plating Processes Subcommitte of the Fabrication Process Committee of IPC,“IPC-4554 Specification for Immersion Tin Plating for Printed Circuit Boards ”., Illinois, IPC, (2007).
15. K. N. Tu, Phys. Rev., B 49, 2030 (1994)
16. B. J. Lee, N. M. Hwang, H. M. Lee, Acta Mater., 45, 1867(1997).
17.NASA Goddard Tin Whisker Website, http://nepp.nasa.gov/whisker/

Chapter 3
1. C. F. Coombs, Jr.,“Printed Circuits Handbook”, 4th ed., New York, McGraw-Hill, (1995).
2. K. N. Tu, Acta Metall., 21, 347(1973).
3. J. W. Mayer, J.M. Poate, and K.N. Tu, Science 190, 228(1975).
4. K. N. Tu, R. D. Thompson, Acta Metall., 30, 947(1982).
5. I. V. Kadija, J. C. Fister, J. Winter, U.S. Patent No.4,749,626(1988).
6. G. S. Bokisa, C. V. Bishop, and J. R. Kochilla, U.S. Patent No.6361823 (2002).
7. J. A. Brusse, G. J. Ewell, and J. P. Siplon, 22nd Capacitor and Resistor Technology Symposium (2002)67.
8. G. S. Bokisa, C. V. Bishop, and J. R. Kochilla, U.S. Patent No.6,361,823(2002).
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11. Zen, J.M., Senthil Kumar, A., Chen, J.C. Electroanalysis, 13, 6, 457(2001).
12. R. Zeng, Z. Pang, H. Zhu, J. Electroanal. Chem., 490, 102(2000).
13. Y. H. Chen, Y. Y. Wang and C. C. Wan, Surf. & Coat. Technol., in press(2007).
14. H.S.White, J.Leddy, and A.J.Bard, J. Am. Chem. Soc., 104 ,4811(1982).
15. S.A.John, and R.Ramaraj, J. Electroanal. Chem., 424 ,49(1997).
16. Taiwan printed circuit association,” Printed Circuits Wet Process Handbook”,1st ed., Tao-Yuan,TPCA(2005).
17. The Plating Processes Subcommitte of the Fabrication Process Committee of IPC,“IPC-4554 Specification for Immersion Tin Plating for Printed Circuit Boards ”., Illinois, IPC, (2007).
18. W. J. Choi, T. Y. Lee, K. N. Tu, N. Tamura, R. S. Celestre, A. A. MacDowell, Y.Y. Bong, and Luu Nguyen, Acta Mater., 51, 6253(2003).
19. B. Z. Lee, and D. N. Lee, Acta Mater., 46, 3601(1998).
20 . L. Hwa-Teng, C. Ming-Hung, Mater. Sci. Eng., A333, 24(2002).

Chapter 4
1. C. F. Coombs, Jr.,“Printed Circuits Handbook”, 4th ed., New York, McGraw-Hill, (1995).
2. Y. H. Chen,”Etching process” Printed Circuits Wet Process Handbook”, 1st ed., Tao-Yuan,TPCA. Chapter 7, 151 (2005).
3. A. M. Soutar, P. T. McGrath, U.S. Patent No.6,860,925(2005).
4. Y. Mikado, Y. Hiramatsu and H. En, U.S. Patent No.6,242,079(2001).
5. J. L. Cordani, U.S. Patent No.4,775,444(1988).
6. D. Huffman, M. Witkowskim., Transactions of The Institute of Metal Finishing 69, 3, 96(1991).
7. E. W. Kinkelaar, P. Golar, U.S. Patent No.4,405,663(1983).
8. A. M. Holtzman, J. Relis, U.S. Patent No. 4,657,632 (1987).
9. D. J. McKenney, A. J. Demaso, K. A. Gosselin, and C. S. Wilson, U.S. Patent No. 6,645,549 (2003).
10. Y. H. Chen,”Immersion tin process” Printed Circuits Wet Process Handbook”, 1st ed., Tao-Yuan,TPCA. Chapter 12, 247 (2005).
11. G. S. Bokisa, C. V. Bishop, and J. R. Kochilla, U.S. Patent No.6,361,823(2002).

Chapter 5
1. C. F. Coombs, Jr.,“Printed Circuits Handbook”, 4th ed., New York, McGraw-Hill, (1995).
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3. A. M. Holtzman, J. Relis, U.S. Patent No. 4,715,894 (1987).
4. A. M. Holtzman, J. Relis, U.S. Patent No. 4,816,070 (1989).
5. A. M. Holtzman, J. Relis, U.S. Patent No. 4,882,202 (1989).
6. J.R.G. Evans and D.E. Packham, J. Adhes. 10 (1979), p. 39.
7. L.J. Slominski and A. Landau, Plating Surf. Finish. 69 (1982), p. 96.
8. B.J. Love, J. Barborowski, M. Charbonner and M. Romand, J. Adhes. 69 (1999), p. 165.
9. B.J. Love and P.F. Packman, J. Mater. Sci. 33 (1998), p. 1359.
10. M. Lebbai, J.K. Kim, W.K. Szeto, M.M.F. Yuen and P. Tong, J. Electron. Mater. 32 (2003), p. 558.
11. J. K. Kim, R. S. C. Woo, Y. P. Hung and M. Lebbai, Surface and coating technology 201(2006)320.
12. M. Lebbai, J.K. Kim and W.K. Szeto, J. Adhes. Sci. Technol. 17 (2003), p. 1543.
13. M. Lebbai, J.K. Kim, W.K. Szeto and J.S. Wu, J. Adhes. Sci. Technol. 18 (2004), p. 983.