中文摘要

近年來由於在汽車、航空、國防等眾多工業上，皆可見到功率積體電路的應用，使功率積體電路(Power Integrated Circuits)在發展上受到越來越多的關注。寬能隙材料常被運用於高功率元件，由於碳化矽(Silicon Carbide)材料在製程上與傳統矽材料相同，在部分製程技術上可使用矽的製程設備，所以在發展上更加受到重視。本篇論文中將著重在橫向高電壓金氧半場效電晶體元件製作於碳化矽材料中的研究及發展上。
本篇論文製作橫向高電壓金氧半場效電晶體，由於RESURF金氧半電晶體量測崩潰時常因閘極場平板崩潰而元件崩潰，為了改善此問題元件設計上採用two-zone RESURF結構，製作上有別於傳統摻雜方式以蝕刻產生two-zone區域，並加入場平板結構且將元件製作於semi-insulating基板以提升崩潰電壓。本論文中設計不同漂移區長度、通道長度、場平板長度及two zone蝕刻位置。由量測結果得知高溫摻雜活化之step bunching現象影響元件導通電阻極大。崩潰上則元件漂移區長度影響最大。在元件最大漂移區長度100μm、通道長度5μm設計下，元件崩潰電壓達4400伏特。元件因通道電子遷移率太差導致導通電阻為19.2Ω-cm2。表面缺陷補陷過大使導通電阻隨溫度上升而減少。

Abstract

In this thesis, we demonstrate a novel high voltage lateral 4H-SiC MOSFET on a semi-insulating substrate with a two-zone RESURF structure to reduce the electric field near the gate oxide. Different from the traditional implanted two zone RESURF structure, we fabricate the two-zone structure by dry etching. Field plates are also employed at the gate and the drain to enhance the blocking voltage. Semi-insulating substrates are used to avoid substrate assisted depletion effect. The length of the drift region, channel, and the etching location of the two zone are designed in this thesis. Experiment results show that step bunching due to the high temperature activation has a significant influence on the on-resistance. The breakdown voltage increases with the drift region and the best achieved blocking voltage is 4400 V, which is the highest value ever reported on SiC lateral MOSFET to the author’s knowledge. Ron is only 19.2Ω-cm2, limited by the poor channel mobility. Ron decreases with temperature in all devices, indicating a large number of interface traps existing.

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