鎖相迴路(Phase-Locked Loop)具有自動同步相位的能力，因而廣泛地被應用於頻率合成以及時脈產生。如同多數電子元件一般，鎖相迴路亦容易受到雜訊干擾，使其輸出訊號產生時間偏移(Jitter)，造成時脈誤差。隨著製程進步，時脈頻率快速增加，系統對時脈正確性要求也越趨於嚴格。量測鎖相迴路輸出訊號的時脈錯誤量，可用來評估其受雜訊干擾的程度，進而作為良品測試的依據。傳統外接量測方法，需仰賴昂貴的測試機臺，花費過高，時間冗長，其量測正確性也易受探針、連接線負載效應影響而降低。
本論文提出二種電路，以內嵌式晶片量測時脈訊號，提供較為快速、低成本的測試方式。其一電路，是利用延遲線(Delay Line)，經由比較待測時脈訊號與其延遲訊號的相位差異，改變延遲線延遲時間，以逼近的方式，求取待測訊號最大週期時脈偏移(Peak-to-Peak Period Jitter)，所提出的量測電路，其可量測頻率範圍為850M至2GHz，粗延遲時間為60.83ps，細延遲時間則為7.98ps，經由HSPICE在0.18μm製程下模擬，模擬最大量測誤差小於5.2ps(0.7LSB)，相較於直接量測取極值方法，本電路能提供更為精確的量測結果；其二電路，則是使用兩級游標震盪器法(Vernier Oscillator Method)量測週期時脈偏移，第一級游標震盪器用於概估時脈週期長度，並產生相應一週期延遲訊號，再以第二級游標震盪器做進一步量測，提供高精度量測，藉由使用二種不同精度游標震盪器，可以有效減少測試時間及內嵌晶片面積支出，電路可量測頻率範圍為800M至2.5GHz，粗精度為116.04ps，細精度則為10.3ps，經由HSPICE在0.18μm製程下模擬，其最大量測誤差小於8ps(0.8LSB)。

In this thesis, we present an on-chip circuit to measure the worst-case period jitter induced by noise for phase-locked loops (PLLs). The circuit uses a digitally controlled delay line to track the extreme period width of the measured signal, thus the worst timing error of the signal can be derived. SPICE simulation results, using 0.18μm CMOS process, show less than 5.2ps (0.7LSB) measurement error at the operation frequency ranging from 850M to 2GHz.
Another circuit, for period jitter measurement, is also provided. It uses two-stage vernier oscillators to transform period jitter of the measured signal into digital words. SPICE simulation results, using 0.18μm CMOS process, show less than 8ps (0.8LSB) measurement error at the operation frequency ranging from 800M to 2.5GHz.

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