對先進製程而言，自對準雙重圖案(SADP)已經成為非常有希望的微影技術之一。在自對準雙重圖案中，疊加層違反(overlay violation)對晶片製造是一個十分關鍵的問題，因此如何有效地減少疊加層違反就變的越來越重要了。此外，大部分現有考慮自對準雙重圖案的實體設計研究都集中在佈局分解和繞線上，只有非常少的研究目標是放在擺置階段。但若是我們能在擺置階段時就得到一個對自對準雙重圖案友善的佈局，那麼在後續佈局修改上的工作就能夠大幅度地減少。

在本篇論文中，我們研究了下面所列出考慮自對準雙重圖案的問題：(1) 可變列寬的單列標準元件細部擺置問題，及(2) 固定列寬的單列標準元件細部擺置問題。在這兩個問題中，疊加層違反都可以透過兩種元件擺置的技術來減少，包括空格插入和元件翻轉。而針對每一個問題，我們都提出了兩個擺置的演算法，第一個演算法只採用了空格插入的技術，而第二個演算法則是同時採用了空格插入和元件翻轉兩種技術。實驗結果顯示我們所提出的演算法皆能有效地減少疊加層違反。

Self-aligned double patterning (SADP) has become one of the most promising lithography techniques for advanced technology nodes. In SADP, overlay violation is a critical issue for fabrication, and therefore the minimization of overlay violation is getting more important. Most of existing SADP-aware physical design works focus on layout decomposition and routing, while only very few attempts are for placement. But if we can generate an SADP friendly layout in the placement stage, the subsequent layout modification efforts will be much more reduced.

In this thesis, we study the following SADP-aware problems: (1) single row cell-based detailed placement with variable row width, and (2) single row cell-based detailed placement with fixed row width. In both problems, overlay violation can be reduced by two cell placement techniques: white space insertion and cell flipping. For each problem, we develop two placement algorithms. The first one adopts only the white space insertion technique, and the second one adopts both white space insertion and cell flipping techniques. Experimental results show that our methods can effectively reduce overlay violation.

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