一個應用於生醫系統低功耗多級共用內建截波器之切換式運算放大器三角積分調變器之設計與製作

簡易檢索 / 詳目顯示

回結果列表

研究生：	蕭釧泓 Hsiao, Chuan-Hung
論文名稱：	一個應用於生醫系統低功耗多級共用內建截波器之切換式運算放大器三角積分調變器之設計與製作 Design and Implementation of a Power-Efficient Stage-Shared Switched-Opamp ΔΣ Modulator with Built-In Choppers for Biomedical Applications
指導教授：	謝志成 Hsieh, Chih-Cheng
口試委員:	陳巍仁 Chen, Wei-Zen 洪浩喬 Hong, Hao-Chiao 闕河鳴 Chiueh, Herming
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2012
畢業學年度：	101
語文別：	英文
論文頁數：	75
中文關鍵詞：	截波穩定、離散時間、切換式放大器、輸入前饋式、低電壓、低功耗、切換式電容電路、三角積分轉換器
外文關鍵詞：	chopper stabilization, discrete-time, switched-opamp, input feedforward, low voltage, low power, switched-capacitor circuit, delta-sigma (ΔΣ) modulation
相關次數：	點閱：1 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

本論文描述一個三階一位元離散時間的三角積分調變器，使用標準0.18-μm互補式金氧半導體製程。切換式運算放大器技術被應用來解決小於一伏特低電壓下MOS開關無法傳遞訊號之問題。使用CRFF架構藉由將輸入訊號直接向前傳遞至量化器輸入端使得各級積分器內的訊號擺幅減小，藉此減少在低電壓下運算互導放大器的規格要求。本論文並提出了一個創新的內建截波器之切換式運算放大器並實現在最前級的積分器內，用來幫助降低放大器內元件不匹配所造成的影響並壓抑1/f雜訊。第二級與第三級積分器共用單一顆運算互導放大器，此多級共用的概念幫助我們減小晶片面積並達到低功耗。
在0.7伏特的工作電壓與256萬赫茲的操作頻率下，此論文所提出的調變器在一萬赫茲的訊號頻寬內，可達到78 dB的信號雜訊及失真比，其中超取樣比為128，以及功率耗損僅有39毫瓦。在這樣的量測結果下得到的FoM為299fJ/conversion-step。總括來說，本論文所提出的多級共用切換式運算放大器之三角積分調變器適合應用於低功耗、高解析度之應用，像是無線可攜式裝置和生醫環境如可攜式、植入式或者甚至拋棄式的醫療產品。

This thesis presents a one-bit third-order discrete-time delta-sigma modulator (DT-ΔΣM) using standard 0.18-μm CMOS process. Switched-opamp (SO) technique is utilized to deal with low supply constraint of sub-1-V operation. The cascade of resonators with distributed feedforward (CRFF) architecture reduces the signal swings of integrators, alleviating the requirement of high slew rate OTAs at low-power operation. A novel chopper-embedded OTA implemented in the first stage effectively eases the impact of component mismatches and suppresses the 1/f noise. The second and third stages share a single OTA. The stage-sharing concept also leads to a smaller die size and a higher power-efficiency.
Operated at 0.7-V supply voltage with 2.56 MHz sampling rate, the proposed modulator achieves 78 dB peak SNDR over a signal bandwidth of 10 kHz with an OSR of 128 and a power dissipation of only 39 μW. The resultant Figure-of-Merit (FoM) is 299 fJ/conversion-step. The proposed SS-SO ΔΣ ADC is suitable for low-power, high-resolution applications like wireless portable devices and bio-signal acquisition.

CONTENTS
ABSTRACT    II
CONTENTS    V
LIST OF FIGURES    VIII
LIST OF TABLES    XI
CHAPTER 1 INTRODUCTION    1
1    MOTIVATION    1
2    THESIS CONTRIBUTION    2
3    THESIS ORGANIZATION    4
CHAPTER 2 BACKGROUND INFORMATION    6
1    ARCHITECTURE SELECTION    7
1.1     Single-Loop Single-Bit ΔΣ Modulator    8
1.2     Single-Loop Multi-Bit ΔΣ Modulator    9
1.3     Multi-Stage Noise-Shaping (MASH) ΔΣ Modulator    10
2    STRATEGY FOR LOW-VOLTAGE (LV) SC ΔΣ MODULATOR    11
2.1     Local Clock-Boosting    11
2.2     Low-VT Device    12
2.3     Switched-Opamp (SO) Technique    13
3    THE EXISTING STATE-OF-THE-ARTS    14
4    SUMMARY    15
CHAPTER 3 SYSTEM-LEVEL DESIGN CONSIDERATION    16
1    STAGE-SHARED SWITCHED-OPAMP (SS- SO) TECHNIQUE    16
2    LOOP TOPOLOGY    19
3    NOISE TRANSFER FUNCTION (NTF)    23
4    NOISE AND OTHER NON-IDEALITIES    27
4.1     Thermal Noise    27
4.1.1    Resistor Thermal Noise    27
4.1.2    Thermal Noise on Capacitor    28
4.1.3    Behavioral Simulation    29
4.2     Flicker Noise    32
4.3     Opamp Finite Gain and GBW    32
4.4     Settling Error    34
4.5     Mismatch and Offset    36
5    SUMMARY    39
CHAPTER 4 PROTOTYPE ΔΣ MODULATOR DESIGN    40
1    OPERATIONAL TRANSCONDUCTANCE  AMPLIFIER (OTA)    40
1.1    gm-Enhancement    41
1.2    Built-In Chopper-Stabilized Switched-OTA (OTA1)    43
1.3    Stage-Shared Switched-OTA (OTA2)    45
2    SINGLE-BIT QUANTIZER    46
3    SAMPLE-AND-HOLD SWITCH    46
4    OTHER SUBCIRCUITS    49
4.1     Non-Overlapping Clock Generator    49
4.2     SR Latch    50
5    COMPLETE MODULATOR CIRCUIT    50
6    SUMMARY    54
CHAPTER 5 CHIP IMPLEMENTATION AND MEASUREMENT    55
1    CHIP IMPLEMENTATION    55
2    MEASUREMENT ENVIRONMENT SETUP    56
3    MEASUREMENT RESULTS    58
4    PERFORMANCE SUMMARY AND COMPARISON    65
5    SUMMARY    67
CHAPTER 6 CONCLUSIONS    68
1    SUMMARY    68
2    FUTURE WORK    69
BIBLIOGRAPHY    71

                                

[1] J. Goes, N. Paulino, H. Pinto, R. Monteiro, B. Vaz, and A. S. Garcao, “Low-power low-voltage CMOS A/D sigma-delta modulator for bio-potential signals driven by a single-phase scheme,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 12, pp. 2595- 2604, Dec. 2005.
[2] J. Johansson, H. Neubauer, and H. Hauer, “A 16-bit 60μW multi-bit ΣΔ modulator for portable ECG applications,” in Proc. Eur. Solid-State Circuit Conf., pp. 161-164, Sept. 2003.
[3] S.-Y. Lee, and C.-J. Cheng, “A Low-Voltage and Low-Power Adaptive Switched-Current Sigma-Delta ADC for Bio-Acquisition Microsystems,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 12, pp. 2628-2636, Dec. 2006.
[4] J. Xu, X. Wu, H. Wang, J. Shen, and B. Liu, “Power optimization of high performance ΔΣ modulators for portable measurement applications,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), pp.1-4, Nov. 2010.
[5] F. Cannillo, E. Prefasi, L. Hernandez, E. Pun, F. Yazicioglu, and C. V. Hoof, “1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition,” in Proc. Eur. Solid-State Circuit Conf., pp. 267-270, Sept. 2011.
[6] D. Zhang, A. Bhide, and A. Alvandpour, “A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1585-1593, July 2012.
[7] L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-μW 88-dB audio sigma-delta modulator in 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1809-1818, Nov. 2004.
[8] M.-G. Kim, G.-C. Ahn, P. K. Hanumolu, S.-H. Lee, S.-H. Kim, S.-B. You, J.-W. Kim, G.C. Temes, and U.-K. Moon, “A 0.9 V 92 dB Double- Sampled Switched-RC Delta-Sigma Audio ADC,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1195-1206, May 2008.
[9] Y. Chae, and G. Han, “Low Voltage, Low Power, Inverter-Based Switched- Capacitor Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 458-472, Feb. 2009.
[10] H. Park, K.-Y. Nam, D. K. Su, K. Vleugels, and B .A. Wooley, “A 0.7-V 870-μW Digital-Audio CMOS Sigma-Delta Modulator,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1078-1088, Apr. 2009.
[11] J. Zhang, Y. Lian, L. Yao, and B. Shi, “A 0.6-V 82-dB 28.6-μW Continuous-Time Audio Delta-Sigma Modulator,” IEEE J. Solid-State Circuits, vol. 46, no. 10, pp. 2326-2335, Oct. 2011.
[12] A. Matsuzawa, “Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment,” IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 470-480, Apr. 1994.
[13] W. Sansen, M. Steyaert, V. Peluso, and E. Peeters, “Toward sub 1V analog integrated circuits in submicron standard CMOS technologies,” in IEEE ISSCC Dig. Tech. Papers, pp. 186-187, 435, Feb. 1998.
[14] L. Yao, M. Steyaert, and W. Sansen, Low-Power Low-Voltage Sigma- Delta Modulators in Nanometer CMOS. New York: Springer, 2006.
[15] C.-H. Hsiao, W.-L. Chen, and C.-C. Hsieh, “A 0.8 V 80.3 dB SNDR Stage-Shared ΔΣ Modulator with Chopper-Embedded Switched-Opamp for Biomedical Application,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2012.
[16] A. P. Chandrakasan, N. Verma, and D. C. Daly, “Ultralow-power electronics for biomedical applications,” Annu. Rev. Biomed. Eng., vol. 10, pp. 247-274, 2008.
[17] J. M. de la Rosa, “Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 1, pp. 1-21, Jan. 2011.
[18] J. Wang, T. Matsuoka, and K. Taniguchi, “A 0.5 V feedforward delta-sigma modulator with inverter-based integrator,” in Proc. Eur. Solid- State Circuit Conf., pp. 328-331, Sept. 2009.
[19] J. Roh, S. Byun, Y. Choi, H. Roh, Y.-G. Kim, and J.-K. Kwon, “A 0.9-V 60-μW 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range,” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 361-370, Feb. 2008.
[20] F. Michel, and M. S. J. Steyaert, “A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 709-721, Mar. 2012.
[21] J. Crols, and M. Steyaert, “Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages,” IEEE J. Solid-State Circuits, vol. 29, no. 8, pp. 936-942, Aug. 1994.
[22] V. Peluso, P. Vancorenland, A. M. Marques, M. S. J. Steyaert, and W. Sansen, “A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1887-1897, Dec. 1998.
[23] J. Sauerbrey, T. Tille, D. Schmitt-Landsiedel, and R. Thewes, “A 0.7-V MOSFET-only switched-opamp ΣΔ modulator in standard digital CMOS technology,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1662-1669, Dec. 2002.
[24] J. Goes, B. Vaz, R. Monteiro, and N. Paulino, “A 0.9V ΔΣ Modulator with 80dB SNDR and 83dB DR Using a Single-Phase Technique,” in IEEE ISSCC Dig. Tech. Papers, pp. 191-200, Feb. 2006.
[25] J. Xu, X. Wu, H. Wang, B. Liu, and M. Zhao, “A 9µW 88dB DR fully-clocked switched-opamp ΔΣ modulator with novel power and area efficient resonator,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), pp. 1-4, Sept. 2010.
[26] C.-H. Kuo, D.-Y. Shi, and K.-S. Chang, “A Low-Voltage Fourth-Order Cascade Delta-Sigma Modulator in 0.18-μm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 9, pp. 2450-2461, Sept. 2010.
[27] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, and A. Baschirotto, “Behavioral modeling of switched-capacitor sigma-delta modulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 50, no. 3, pp. 352- 364, Mar. 2003.
[28] K.-Y. Nam, S.-M. Lee, D. K. Su, and B. A. Wooley, “A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1855- 1864, Sept. 2005.
[29] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. Chichester: Wiley, 2005, pp. 107-111.
[30] B. Razavi, Design of Analog CMOS Integrated Circuits. 1st ed. New York, NY: Mcgraw-Hill, 2001.
[31] A. M. Abo, and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
[32] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010.
[33] P. E. Allen, CMOS Analog Circuit Design. New York: Oxford, 2002, ch. 10.
[34] B. Murmann, “ADC Performance Survey 1997-2012,” [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.
[35] K.-P. Pun, S. Chatterjee, and P. R. Kinget, “A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to- Open DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 496-507, Mar. 2007.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文