系統單晶片(system-on-chip, SOC)可以整合數位、記憶體、類比、甚至是天線元件於同一個晶片中。在測試系統單晶片時，自動測試設備(automatic test equipment, ATE)將需要比上一個世代的測試機台擁有更高的操作頻率、更多的測試針腳、以及更好的時間準確度。這個趨勢大幅地提升了自動測試設備的設計複雜性。

為了要解決在目前自動測試設備所面臨的成本與效能的問題，我們推出了后羿測試方法。后羿測試方法有兩大主要功能：第一，使用無線的方式收發測試資料；第二，使用嵌入式測試模組。然而，由於后羿測試方法是一個嶄新的測試方式並且將大幅地改變目前測試的基礎建設，我們在發展之前需要有一個詳盡的成本與效能的分析。

在這篇論文中，我們將概要地介紹后羿測試系統，並且提出一個測試成本模型來比較后羿測試方法與目前主流的測試方法。我們以五百一十二百萬位元(Mb)的第二代雙倍資料率同步動態隨機存取記憶體(DDR2 SDRAM)做為第一個基本範例，發現后羿測試方法的測試成本比主流測試方法的測試成本要少百分之七十四。

第二個範例我們選用網路加密處理器。我們發現雖然后羿測試成本依然比主流測試成本要低，不過僅僅降低百分之二十一。詳細比較其中差異發現原因在於后羿測試成本中有百分之九十三是花費在邏輯自我測試電路的製造成本上。如果我們可以降低邏輯自我測試電路的面積的話，我們將可以在后羿測試方法上獲得更多的利益。

第三個範例是延伸自第二個範例。差別在於假設主流測試方式中，網路加密處理器也使用邏輯自我測試電路來測試。后羿測試方法依然比主流測試方法降低百分之五十六的測試成本。我們發現探針卡費用在這次的範例中成為降低主流測試成本的瓶頸。尤其在縮短平均測試時間之後，探針卡費用將成為主流測試方法的主要花費。

另外，我們分析了不同的製程、額外面積花費、待測晶片的大小、生產量以及平均測試時間在不同的範例中對於測試成本模型的影響。於實驗結果部分，我們也將介紹最新版本的后羿測試機台原型，這佐證了后羿測試方法的可行性。

The SoC designs can integrate digital, memory, analog, and even RF components on the same chip. This trend greatly complicates the design of automatic test eauipment (ATE), which has to test all the components of the SoC, with higher frequency, pin count, and timing accuracy as compared with previous-generation ATEs.

To address the cost and performance issues faced by conventional ATE, the HOY approach has been proposed, with two main features. One is wireless test access, and the other is embedded test. However, since HOY is a new methodology that will likely change the entire infrastructure, a detailed analysis of its cost and performance figures is necessary before deployment.

In this thesis, we briefly present the HOY test system, then propose a test cost model to compare the HOY approach and the conventional test method. In a 512Mb DDR2 DRAM case, the test cost of HOY method is reduced by 74% compared with the conventional test method.

The second example is a network security processor. Although in this particular case the test cost of HOY method is reduced by 21% compared with the conventional test mehod, 93.12% of test cost is spend on area overhead caused by logic BIST. If we reduce the area overhead of logic BIST, it will gain more benefit by using the HOY method.

The third example is the extended version of the second example. It assumes the DUT has its own logic BIST in conventional test. The test cost of HOY method is reduced by 56% compared with the conventional test method. We found that the probe card cost becomes the bottleneck of conventional test. The ratio of probe card cost increases when the test time decrease.

In addition, we analyze the test cost model with respect to different manufacturing process, area overhead, die size, manufacturing volume, and test time. Results are shown for a latest HOY prototype.

[1]T.-W.Ko, Y.-T. Hsing, C.-W. Wu and C.-T. Huang, "Stable perfoermance MAC protocol for HOY wireless tester under large population" in Proc. Int'l Symp. on VLSI Design, Automaiton , and Test, Hsinchu, Apr. 2007, pp.160-163
[2]Semiconductor Industry Association, "International technology roadmap for semiconductors (ITRS), 2005 edition," Seoul, Korea, Dec. 2005
[3]H. Eberle, A. Wander, and N. Gura, "Testing systems wirelessly," in Proc. IEEE VLSI Test Symp., Napa Valley, Apr. 2004, pp.335-340
[4]D. Zhao, S. Upadhyaya, and M. Maragala, "A new destributed test control architecture with multihop wireless test connectivity and communication for gigahertz system-on-chip," in Proc. IEEEE Noth Atlantic Test Workshop, New York, May 2003, pp. 90-93
[5]C. Sellathamby, M. Reja, F. Lin, B. Bai, E. Reid, S. Slupsky, I. Filanovsky, and K. Iniewski, "Noncontact wafer probe using wireless probe cards," in Proc. Int'l Test Conf., Austin, Nov. 2005, pp. 447-452.
[6]J. Gatej, L. Song, C. Pyron, R. Raina, and T. Munns, "Evaluating ATE features in terms of test escape rates and other cost of test culprits," in Proc. Int'l Test Conf., Baltimore, Oct. 2002, pp.1040-1049.
[7]R. Rajsuman, N. Masuda, and K. Yamashita, "Architecture and design of an open ATE to incubate the development of third-party instruments," IEEE Trans. on Instrumentation and Measurement, vol. 54, no. 5, pp. 1678-1698, Oct. 2005.
[8]H. Eberle, "Radioport: a radio network for monitoring and diagnosing computer systems," in Proc. Symposium on High Performance Interconnects, Stanford, Aug. 2002, pp.135-139.
[9]H. Eberle, "A radio network for monitoring and diagnosing computer systems," IEEE Micro, vol.23, no. 1, pp. 60-65, Jan.-Feb. 2003.
[10]D. Zhao, S. Upadhyaya, and M. Margala, "Control constrained resource partitioning for complex SoCs intra-chip wireless interconnects," in Proc. IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, Boston, Nov. 2003, pp. 425-432.
[11]D. Zhao and S. Upadhyaya, "A generic resource distribution and test scheduling scheme for embedded core-based SoCs," IEEE Trans. on Instrumentation and Measurement, vol. 53, no.2, pp. 318-329, Apr.2004.
[12]D. Zhao, An Integrated Framework for Concurrent Test and Wireless Control in Complex SoCs. State University of New York at Buffalo: Ph.D. dissertation, 2004.
[13]D. Zhao, S. Upadhyaya, and M. Margala, "A new SoC test architecture with RF/wireless connectivity," in Proc. European Test Symposium, Tallinn, May 2005, pp.14-19.
[14]D. Zhao and S. Upadhyaya, "Dynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing," IEEE Trans. on Computer-Aided Design of Integrated Circuts and Systems, vol.24, no.6, pp. 956-965, June 2005.
[15]D. Zhao,S. Upadhyaya, and M. Margala, "Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no.7, pp. 1411-1418, July 2006.
[16]B. Moore, C. Backhouse, and M. Margala, "Design of wireless on-wafer submicron characterization system," in Proc. IEEE VLSI Test Symp., Napa Vally, Apr. 2004, pp. 341-346.
[17]B. Moore, M. Margala, and C. Backhouse, "Desin of wireless on-wafer submicron characterization system," IEEE Trans. on VLSI Systems, vol.13, no.2, pp. 169-180, Feb. 2005.
[18]B. Moore, C. Sellathamby, P. Cauvet, H. Fleury, M. Reja, L. Fu, B. Bai, E. Reid, I. Filanovsky, and S. Slupsky, "High throughput non-contact SiP testing," in Proc. Int'l Test Conf., Santa Clara, Oct. 2007, pp.1-10.
[19]B. Moore, M. Mangrum, C. Sellathamby, M. Reja, T. Weng, B. Bai, E. Reid, I. Filanovsky, and S. Slupsky, "Non-contact testing for SoC and RCP (SIPs) at advanced nodes," in Proc. Int'l Test Conf. (ITC). Santa Clara, Oct. 2008, pp. 1-10.
[20] B. MOore, C. Sellathamby, S. Slupsky, and K. Iniewski, "Chip to chip communications for terabit transmission rate," in Proc. IEEE Asia Pacific Conference on Circuits and Systems, Macao, Nov. 2008, pp. 1558-1561.
[21] E. Marinissen, D.-Y.Lee, J. Hayes. C. Sellathamby, B. Moore, S. Slupsky, and L. Pujol, "Contactless testing: Possibility or pipe dream?" in Proc. Conf. Design, Automation, and Test in Europe (DATE), Nice, Apr. 2009, pp.676-681.
[22] M. Chang, V. Roychowdhury, L. Zhang, H. Shin, and Y.Qian, "RF/Wireless interconnect for inter- and intra-chip communications," Proceedings of the IEEE, vol.89, no.4, pp. 456-466, Apr. 2001.
[23]B. Floyd, A CMOS wireless interconnect system for Multigigahertz clock distribution. University of Florida at Gainesville: Ph.D. dissertation, 2001.
[24]B. Floyd, C. Hung, and K. O, "Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters," IEEE Jour. of Solid-State Circuits, vol.37, no.5, pp.543-552, May 2002.
[25]C.-W. Wu, C.-T. Huang, S.-Y. Huang, P.-C. Huang, T.-Y.Chang, and Y.-T. Hsing, "The HOY tester-Can IC testing go wireless?" in Proc. Int'l Symp. on VLSI Design, Automation, and Test, Hsinchu, Apr. 2006, pp.183-186
[26]P.-K. Chen, Y.-T.Hsing, and C.-W.Wu, "On feasibility of HOY-awireless test methodology for VLSI chips and wafers," in Proc. Int'l Symp. on VLSI Design, Automation, and Test, Hsinchu, Apr. 2006, pp.243-246
[27]J.-J. Liou, C.-T. Huang, C.-W. Wu, C.-C. Tien, C.-H. Wang, H.-P. Ma, Y.-Y. Chen, Y.-C. Hsu, L.-M. Deng, C.-J. Chiu, Y.-W. Li, and C.-M. Chang, " A prototype of a wireless-based test system," in Proc. IEEE Int. SOC Conf., Sept. 2007, pp. 225-228.
[28]J.-M. Lu and C.-W. Wu, "Cost and benefit models for logic and memory BIST," in Proc. Conf. Design, Automation, and Test in Europe, Paris, Mar. 2000, pp.710-714.
[29]R.-F. Huang, C.-H. Chen, and C.-W. Wu, "Economic aspects of memory built-in self-repair," IEEE Design & Test of Computers, vol.24, no.2, pp. 164-172, Mar.-Apr. 2007.
[30]M.-Y. Chu. T.-Y. Chang, H.-J. Hsu, C.-Y. Lee, C.-F. Li, H.-P. Ma, C.-T. Huang, and P.-C. Huang, "Wireless communications interface design for HOY wireless testing scheme," in Proc. International Test Synthesis Workshop, Santa Barbara, Apr. 2008.
[31]J. I. Capetanakis, "Tree algorithm for packet broadcast channels," IEEE Trans. on Informaation Theory, vol.25, pp. 505-515, Sept. 1979.
[32]M. Sidi and I. Cidon, "Splitting protocols in presence of capture," IEEE Trans. on Informaiton Teory, vol.31,pp.295-301, Mar. 1985.
[33]R. Rom and M. Sidi, Multiple-Access Protocols. "NEW YORK": Springer-Verlag, 1990.
[34]IEEE, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications. Piscataway: IEEE Standards Department, Aug.1999.
[35]P. Nag, A. Gattider, S. Wei, R. Blanton, and W. Maly, "Modeling the economics of testing: a DFT perspective," IEEE Design & Test of Computers, vol.19, no. 1, pp. 29-41, Jan.-Feb. 2002.