隨著時代的演進,現代社會在生醫領域的研究日趨重視,而長時間在人體表皮層下的生醫探測人體狀況的晶片也漸漸被需要,而類比記憶體常出現在生醫晶片中,用來記錄長時間晶片學習記錄人體情況的結果.
此研究的主要目標是在標準0.35微米互補型金氧半製程下,設計出聰明可動態雙向線性調適的高解析非揮發性類比記憶體,而設計方向則是側重雙向調適,線性,高解析度,操作簡易,快速完成寫入,並觀測其在長時間常態溫度下記憶體儲存的有效時間常度.
研究中從以HSPICE建構能夠模擬出熱電子熱電洞特性的合理模型,進而模擬類比記憶體的電路特性,以此條件下模擬設計出電壓型可雙向線性調適,並具有超過8位元解析度的類比記憶體.再經由下線後得到量測晶片的量測數據與HSPICE電路模擬結果做比較,檢測晶片之特性是否符合HSPICE模擬的結果.
當記憶體單元的特性量測結果與模擬情況符合後,就接續著模擬並下線記憶體陣列晶片,設計以及量測針對此電壓型雙向線性調適非揮發性記憶體的陣列,用以驗證個別記憶體單元間寫入是否會彼此干擾的情況,並在此晶片量測寫入速度加快的結果是否符合預期結果.最後則是做資料保存(data-retention)的量測,記憶體儲存值以儲存三個月以上為目標時間,藉由資料保存相關理論以實驗數據求得長時間的記憶體儲存值情況.並且改善加快寫入速度.當資料保存量測與理論驗證後,接著研究方向朝陣列架構的電路模擬與下線.
最後,隨著研究過程的推進,各式各樣的問題以及現象隨之浮現,在本研究的最後部分會提出並給予一些想法與解決情形來討論總結.

Floating-gate devices have been widely used in many commercial products as memory cells. In this paper, a bidirectionally-programmable non-volatile analog storage cell has eight effective resolutions to write or erase information. The memory cell, which stores the analog information in the MOS transistor floating-gate device, is written and erased by means of hot-electron injection and hot-hole injection. The memory circuit can write or erase the target value to the floating-gate devices and it is achieved by a simple, on-chip comparator. By using a comparator, the circuit controls the programming mechanisms automatically that the storage analog information can be programmed to the target value precisely under negative feedback. Errors due to the effects of device mismatches or trapping can be eliminated by the feedback control. By modeling the programming mechanisms, the proposed analog memory circuit is designed and can be used in analog neural networks. The proposed analog memory circuit has the storing voltage range from 0.6V to 2.2V and the error voltage less than 5mV. In this experiment, data-retention should be tested after the design of the memory cell was finished. the data-retention test results can be used to estimate the storage time in which the memory cell holds the storage information. In the end, a memory-cell array is designed by using floating-gate technique to store analog information.

[1]褚明儒,「擴散網路」晶片系統神經元的超大型積體電路設計,碩士論文,國立清華大學,2005.
[2]盧峙丞,連續值局限型波茲曼模型積體電路系統之模組化及程式化設計,博士論文,國立清華大
學,2010.
[3]施敏,半導體元件物理與製作技術(第二版),2007.
[4]K. Lee and Y. King, “New single-poly EEPROM with cell size down to 8F2 for high density embedded
nonvolatile memory applications,” in VLSI Technology Symposium,Kyoto, Japan, 2003, pp. 93–94.
[5]K. Rahimi, C. Diorio, C. Hernandez, and M. Brockhausen, “A simulation model for floating-gate MOS
synapse transistors,” in IEEE International Symposium on Circuits and Systems. Citeseer, 2002.
[6]S. Tam, P. Ko, and C. Hu, “Lucky-electron model of channel hot-electron injection in MOSFET’s,” IEEE
Transactions on Electron Devices, vol. 31, no. 9, pp. 1116–1125,2005.
[7]黃正達,高解析度非揮發性類比記憶體研究發展,碩士論文,國立清華大學,2007.
[8]T. Ong, P. Ko, and C. Hu, “Hot-carrier current modeling and device degradation in surface-channel
p-MOSFETs,” IEEE Transactions on Electron Devices, vol. 37, no. 7, pp. 1658–1666, 2002.
[9]W. Weber and F. Lau, “Hot-carrier drifts in submicrometer p-channel MOSFET’s,” Electron Device
Letters, IEEE, vol. 8, no. 5, pp. 208–210, 2005.
[10]K. Lee, S. Wang, and Y. King, “Self-convergent scheme for logic-process-based multilevel/analog
memory,” IEEE Transactions on Electron Devices, vol. 52, no. 12,pp. 2676–2681, 2005.
[11]C. Diorio, D. Hsu, and M. Figueroa, “Adaptive CMOS: from biological inspiration to
systems-on-a-chip,” Proceedings of the IEEE, vol. 90, no. 3, pp. 345–357, 2002.
[12]C. Diorio, P. Hasler, B. Minch, and C. Mead, “A floating-gate MOS learning array With locally
computed weight updates,” IEEE Transactions on Electron Devices, vol. 44,no. 12, pp. 2281–2289, 2002.
[13]P. Hasler, “Continuous-time feedback in floating-gate MOS circuits,” IEEE Transactions on Circuits
and Systems II: Analog and Digital Signal Processing, vol. 48, no. 1,pp. 56–64, 2002.
[14]C. Diorio, P. Hasler, B. Minch, and C. Mead, “A complementary pair of four-terminal silicon synapses,”
Analog Integrated Circuits and Signal Processing, vol. 13, no. 1, pp.153–166, 1997.
[15]C. Diorio, S. Mahajan, P. Hasler, B. Minch, and C. Mead, “A high-resolution nonvolatile analog
memory cell,” in Circuits and Systems, 1995. ISCAS’95., 1995 IEEE International Symposium on, vol. 3.
IEEE, 2002, pp. 2233–2236.
[16]M. Figueroa, S. Bridges, and C. Diorio, “On-chip compensation of device-mismatch effects in analog
VLSI neural networks,” in Advances in neural information processing systems 17: proceedings of the 2004
conference. The MIT Press, 2005, p. 441.
[17]G. Serrano, “High Performance Analog Circuit Design Using Floating-Gate Techniques,”Ph.D.
dissertation, Citeseer, 2007.
[18]C. Bleiker and H. Melchior, “A four-state EEPROM using floating-gate memory cells,” IEEE Journal of
Solid-State Circuits, vol. 22, no. 3, pp. 460–463, 2002.
[19]K. Hasnat, C. Yeap, S. Jallepalli, S. Hareland, W. Shih, V. Agostinelli, A. Tasch, and C.Maziar,
“Thermionic emission model of electron gate current in submicron NMOSFETs,” IEEE Transactions on
Electron Devices, vol. 44, no. 1, pp. 129–138, 2002.
[20]K. Sato, K. Kenmizaki, S. Kubono, T. Mochizuki, H. Aoyagi, M. Kanamitsu, S. Kunito,H. Uchida, Y.
Yasu, A. Ogishima et al., “A 4-Mb pseudo SRAM operating at 2.6 1 V with 3-uA data retention current,”
IEEE Journal of Solid-State Circuits, vol. 26, no. 11,pp. 1556–1562, 2002.
[21]H. Uh, J. Lee, Y. Ahn, S. Lee, S. Hong, J. Lee, G. Koh, G. Jeong, T. Chung, and K. Kim, “A strategy for
long data retention time of 512 Mb DRAM with 0.12 um design rule,” in VLSI Technology, 2001. Digest of
Technical Papers. 2001 Symposium on. IEEE, 2002,pp. 27–28.
[22]A. Kordesch, S. Awsare, J. Brennan Jr, P. Guo, M. Hemming, M. Herman, P. Holzmann, E. Ng, C. Liu,
K. Su et al., “The reliability of multilevel analog memory in a voice storage and playback system using
source-side injection flash,” in VLSI Technology, Systems, and Applications, 1999. International Symposium
on. IEEE, 2002, pp. 266–269.
[23]J. Brewer and M. Gill, “Nonvolatile memory technologies with emphasis on flash,” IEEE
Whiley-Interscience, Berlin, 2007.
[24]R. Harrison, J. Bragg, P. Hasler, B. Minch, and S. Deweerth, “A CMOS programmable analog
memory-cell array using floating-gate circuits,” IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, vol. 48,no. 1, pp. 4–11, 2002.
[25]S. Kinoshita, T. Morie, M. Nagata, and A. Iwata, “A PWM analog memory programming circuit for
floating-gate MOSFETs with 75-us programmming time and 11-bit updating resolution,” IEEE Journal of
Solid-State Circuits, vol. 36, no. 8, pp.1286–1290, 2002.
[26]J. Goldberg and M. Sandler, “Pseudo-natural pulse width modulation for high accuracy
digital-to-analogue conversion,” Electronics Letters, vol. 27, no. 16, pp.1491–1492, 2008.
[27]B. De Salvo, G. Ghibaudo, G. Pananakakis, B. Guillaumot, P. Candelier, and G. Reimbold,“A new
physical model for NVM data-retention time-to-failure,” in Reliability Physics Symposium Proceedings,
1999. 37th Annual. 1999 IEEE International.IEEE, 2002, pp. 19–23.
[28]M. Janai, B. Eitan, A. Shappir, E. Lusky, I. Bloom, and G. Cohen, “Data retention reliability model of
NROM nonvolatile memory products,” IEEE Transactions on Device and Materials Reliability, vol. 4, no. 3,
pp. 404–415, 2004.
[29]P. Layton, L. Longden, and E. Patnaude, “Evaluation of reliability and data retention of an irradiated
nonvolatile memory,” in Radiation and Its Effects on Components and Systems, 2005. RADECS 2005. 8th
European Conference on. IEEE, 2007.