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研究生: 林祐民
Yo-Min Lin
論文名稱: 以FPGA為基礎之WiMAX上鏈接收機設計實現與測試
FPGA-based WiMAX Uplink Receiver Design, Implementation and Testing
指導教授: 鐘太郎
Tai-Lang Jong
丁原梓
Yuan-Tzu Ting
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 112
中文關鍵詞: 無線通訊WiMAX實體層正交多頻分工
外文關鍵詞: WiMAX, OFDM, PHY, 802.16d
相關次數: 點閱:2下載:0
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  • 無線通訊系統在近幾年來的發展非常迅速,其傳輸速率(Data Rate)與品質的需求也不斷提昇,而正交分頻多工(Orthogonal Frequency Division Multiplexing, OFDM)的調變技術,由於對頻譜的使用效率較高,因此能提供較高的傳輸速率;另外此技術較能抵抗無線通道的多路徑衰減(Multipath Fading),有助於提昇傳輸品質,因此非常適合應用在目前的都會區環境。

    在眾多應用於都會區無線網路的規格裡,WiMAX系統提供了高速、長程與高品質的傳輸,其中802.16d與802.16e分別是固定式與移動式的系統,本論文的研究主要是以固定式的系統為主,根據IEEE 802.16-2004 WirelessMAN-OFDM實體層(Physical Layer)規格,設計上鏈收發機系統之硬體電路,將其實現於FPGA上,並透過閉路(Close Loop)測試,實際將用戶發射端產生的類比訊號送給基地台接收端;另一方面為了實際驗證本系統,在個人電腦端設計了基本的MAC(Medium Access Control)層管理程式,以方便對實體層進行各種設定;最後利用PPC(Power PC)建立溝通介面,將FPGA與個人電腦銜接起來,完成一套可以自行收發資料的通訊系統。

    本論文之貢獻在於將WiMAX上鏈系統實際呈現在一個具有FPGA與PPC的發展版上,並提供基本的MAC層控制,讓使用者能在PC端控制並驗證此系統。而本系統上所有模組化的電路設計,也能方便使用者自行研發效能更好的模組來進行抽換,為之後的研究者提供了一個完整的硬體測試環境。


    Wireless communications is a rapidly growing industry nowadays. As the requirement of transmission rate and quality is higher and higher, more related researches are developed. The technique of OFDM is proposed with some benefits. The higher spectral efficiency provides higher transmission rate. Besides, OFDM can reduce the distortion due to multi-path fading to improve the transmission quality. These advantages make OFDM to be a suitable technique for typical metropolis environment.

    In several communication standards, WiMAX provides the higher data rate, the farther transmission distance, and the better communication quality. In this thesis, we implement a uplink WiMAX transceiver on a development board with FPGA and PPC based on the IEEE 802.16-2004 WirelessMAN-OFDM standard which is used for fixed transmission applications. The physical layer architecture is accomplished on the FPGA. On the other hand, the basic MAC is achieved with the PPC to provide the communication interface between PC and FPGA. This system can be verified by the close loop testing, that is, transmit analog signal generated by subscriber station transmitter to the base station receiver on the same board. Then we can send the transmission data from PC to this system, and get the decoded result back.

    The contribution of this thesis can be summarized as follows. We implemented the uplink WiMAX system on the development board with FPGA and PPC. Users can control and verify this system from PC conveniently. Besides, the modularly designed structure makes users do any modifications easily. This provides an integrated hardware platform for the further researchers.

    1. 簡介 1 1.1. 研究背景 1 1.2. 研究主題 2 1.3. 論文架構 3 2. OFDM系統傳輸架構 4 2.1. 符元基本架構 4 2.1.1. 頻域 4 2.1.2. 時域 5 2.2. 碼框架構(Frame Structure) 6 2.2.1. 前置訊號(Preamble) 7 2.2.2. 碼框控制檔頭(Frame Control Header) 8 2.2.3. 廣播訊息(Broadcast messages) 9 2.3. 發射端規格 9 2.3.1. 補空與隨機編碼(Padding and Randomization) 10 2.3.2. 里得所羅門編碼(Reed Solomon Code Encoding) 11 2.3.3. 迴旋編碼與壓縮(Convolutional Code Encoding and Puncturing) 13 2.3.4. 位元交錯(Interleaving) 14 2.3.5. 子載波調變(Subcarrier Mapping) 15 2.3.5.1. 資料子載波(Data Subcarrier) 15 2.3.5.2. 領航子載波(Pilot Subcarrier) 16 2.3.6. 反傅立葉轉換與循環字首(IFFT and CP Addition) 17 2.3.7. 時空碼(Space Time Code) 17 2.4. 通道模型(Channel Model) 18 2.5. 接收端訊號處理 20 3. 接收端架構設計理論說明 22 3.1. 封包偵測(Symbol detection) 22 3.2. 載波頻率偏移估測(Frequency Offset Estimation) 24 3.3. 通道響應估測(Channel Estimation) 26 3.4. 載波相位追蹤(Carrier Phase Tracking) 26 3.5. 子載波解調(Subcarrier Demapping) 28 3.6. 迴旋解碼(Convolutional Code Decoding) 32 3.7. 里得所羅門解碼(Reed Solomon Code Decoding) 35 3.8. 時空解碼(Space Time Code Decoding) 35 4. 軟體模擬 39 4.1. 封包偵測 39 4.2. 載波頻率偏移估測 40 4.3. 通道效應估測 41 4.4. 載波相位追蹤 42 4.5. 資料子載波解調 43 4.6. 系統效能 46 4.7. 定點數系統效能 47 4.8. BS天線分集系統效能 50 5. 硬體架構設計與實現 54 5.1. 用戶發射端架構設計 54 5.1.1. 隨機編碼 56 5.1.2. RS-CC編碼 57 5.1.3. 位元交錯 58 5.1.4. 訊號調變與反傅立葉轉換 60 5.1.5. 時域訊號合併 61 5.1.6. 控制電路設計 61 5.2. 用戶發射端模擬結果 65 5.2.1. 硬體資源使用與時間限制 65 5.2.2. 功能驗證 66 5.3. 基地台接收端架構設計 70 5.3.1. 封包偵測 70 5.3.2. 載波頻率偏移偵測與補償 73 5.3.3. 傅立葉轉換 75 5.3.4. 通道效應偵測與補償 76 5.3.5. 載波相位追蹤 79 5.3.6. 子載波解調與後續解碼 80 5.3.7. 控制電路設計 80 5.4. 接收端模擬結果 85 5.4.1. 硬體資源使用與時間限制 85 5.4.2. 功能驗證 86 5.4.2.1. 通道效應偵測功能驗證 87 5.4.2.2. 訊號解調前之功能驗證 88 5.4.2.3. 接收端時間設計驗證 91 5.4.2.4. 接收端解碼驗證 93 6. 系統整合與人機界面 97 6.1. 系統平台介紹 97 6.2. 系統平台建立 98 6.2.1. 硬體平台建立 99 6.2.2. 軟體平台建立 100 6.3. 軟韌體程式設計 100 6.4. 人機介面設計 102 6.5. 系統整合驗證 103 6.6. 系統發展環境展示 107 7. 結論與未來展望 108 8. 參考文獻 110

    [1] IEEE 802.16-2004, "IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed Broadband Wireless Access Systems," IEEE Std., 2004
    [2] 802.16 Broadband Wirelss Access Working Group, "Channel Models for Fixed Wireless Applications, ", IEEE 802.16.3 Std. , 2001
    [3] T.M. Schmidl and D.C.Cox, "Robust frequency and timing synchronization for OFDM," IEEE Transactions on Communicatoin, vol.45, pp.1613-1621 , 1997
    [4] Bo Ai, Zhi-xing Yang, Chang-yong Pan, Jian-hua Ge, Yong Wang, Zhen Lu, "On the Synchronization Techniques for Wireless OFDM Systems," IEEE Transactions on Broadcasting, vol.52, No. 2, pp.236-244, June 2006
    [5] H. Meyr, M. Moeneclaey, S. Fechtel, "Digital Communication Receivers : Synchronization, Channel Estimation, and Signal Processing," Wiley, 1997
    [6] Jun Wu, Qun Zhou, Cheng, K.K.M., "The adaptive algorithm of symbol timing and carrier phase estimation in OFDM systems," Communications, 2001. ICC , 2001. IEEE International Conferrence on vol. 1, pp.156-160,11-14 June 2001
    [7] C. Berrou, P. Adde, E. Angui, and S. Faudeil, "A low complexity soft-output Viterbi decoder architecture," in Proc. IEEE Int. Conf. Communications, pp. 737-740, 1993
    [8] J. Hagenauer and P. Hoeher, "A Viterbi algorithm with soft-decision outputs and its applications," in Proc. IEEE GLOBECOM, Dallas, Texas, pp.47.11–47.17, Nov. 1989
    [9] 李安堯, "FPGA-based Outer Receiver Design and Implementation for WiMAX," 國立清華大學碩士論文, 2006

    [10] Kuang Yung Liu, "Architecture for VLSI design of Reed-Solomon decoders," IEEE Transcations on computers, February 1984
    [11] Branka Vucetic, Jinhong Yuan, "Space-Time Coding," Wiley Publisher, 2003
    [12] Swartzlander, Young, Joseph, "A Radix 4 DelayCommutator for Fast Fourier Transform Processor Implementation," IEEE J.Solid-State Circuits, Vol.SC-19, pp.702-709, October 1984
    [13] Ching-Hsien Chang, Chin-Liang Wang, Yu-Tai Chang, "A novel memory-based FFT processor for DMT/OFDM applications," IEEE International Conference on Acoustics, Speech, and Signal, pp.1921-1924, 15-19 March 1999
    [14] Sang-Chul Moon, Ln-Cheol Park, "Area-Efficient Memory –Based Architecture for FFT Processing," IEEE Int. Symp. On Circuits and Systems, pp.101-104, 25-28 May 2003
    [15] C. S. Burrus, "Index mappings for multidimensional formulation of the DFT and convolution," IEEE Trans., vol ASSP-25, pp.239-242, June 1977
    [16] 陳博奇, "FPGA-based Inner Receiver Design and Implementation for WiMAX,"國立清華大學碩士論文,2006
    [17] Xilinx, "Libraries Guide," Xilinx ISE 6.3i Documentation, August 20, 2004
    [18] Sreeraman Rajan, Sichun Wang, Robert Inkol, and Alain Joyal, "Efficient Approximations for the Arctangent Function," IEEE Signal Processing Magazine, pp.108-111, May 2006
    [19] P. Duhamel, B. Piron, and J. M. Etcheto, "On computing the inverse DFT," IEEE Trans. Acoust., Speech and Sig. Processing, 36 (2): 285–286 , 1988
    [20] Ray Andraka, "A survey of CORDIC algorithms for FPGA based computers", Proceedings of the 1998 ACM/SIGDA sixth international symposium on FPGA, Monterey, CA. p191-200(session 9, Novel FPGA Applications) , 1998
    [21] Deprettere, E., Dewilde, P., and Udo, R., "Pipelined CORDIC Architecture for Fast VLSI Filtering and Array Processing," Proc. ICASSP’84, pp.41.A.6.1- 41.A.6.4, 1984
    [22] Hsiao, S.F. and Delosme, J.M., "The CORDIC Householder Algorithm," Proceedings of the 10th Symposium on Computer Arithmetic, pp.256-263, 1991
    [23] Xilinx, "Platform Studio User Guide," Embedded Development Kit EDK 6.3i Documentation , August 20, 2004
    [24] Xilinx, "Getting Started with EDK," Embedded Development Kit EDK 6.3i Documentation , August 20, 2004
    [25] Xilinx, "EDK OS and Libraries Reference Manual," Embedded Development Kit EDK 6.3i Documentation , August 20, 2004
    [26] Xilinx, "Embedded System Tools Reference Manual," Embedded Development Kit EDK 6.3i Documentation , August 20, 2004
    [27] MontaVista Software, Inc., "MontaVista Linux Professional Edition 3.1 Installation Guide," March 3,2004
    [28] Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman, "Linux Device Drivers,Third Edition," 2005

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