本篇論文介紹一個以DLX架構為基礎的嵌入式處理器,其擁有執行ARM指令集的能力,亦可使用ARM處理器的相關發展工具.DLX架構是一種廣泛被使用於處理器設計的架構,其主要有四項特點:一種特殊的載入/儲存架構,固定長度且有效率的指令格式,易於加入管線設計的結構,程式碼的編譯非常簡捷.今日在嵌入式處理器領域中,ARM以龐大的佔有率取得領導的地位,它所製作的處理器的架構除了包含DLX的基本特點外,其指令集內含有一些特別的功能如下:有條件式的執行程式,各種中斷程序的處理,以及支援六種的操作模式.綜合上述兩種架構的特點,我們以最為普及的DLX架構作為處理器的設計主體,依據不同情況與需求加以修改,使其達到可實現ARM指令集的各種執行功能.此外,有鑒於電路設計的日趨複雜,測試位於處理器核心深處之嵌入式模組的困難度也跟著增加,在此我們也提供一種以軟體程式運作為基礎,可達到相當高的錯誤涵蓋率的自我測試方法,再搭配部分串鏈的測試技術,藉此達到百分之百的錯誤涵蓋率.與傳統上以完整串鏈技術作為測試方法不同之處,採用兩種測試方法的好處是,一方面可以在不減少錯誤涵蓋率下,大幅降低加入測試電路所造成的設計面積增加,一方面又仍能確保我們的設計正確無誤地運作.最後,我們設計此處理器的目的主要著眼於系統整合設計上的測試研究,作為各種測試模擬與應用的環境平台.

An embedded processor based on the DLX architecture is introduced in this thesis. It is designed with the capability of performing ARM instruction set and is also supported by these toolkits, which are developed for the ARM. We name the processor as "DLX based Arm instruction set Processor" (DAP). Depending on the features of both DLX and ARM architecture, the DAP invokes the load-store architecture, fixed legth instruction set, pipeline capability, conditional execution and exceptions. Due to the difficulty of testing of embedded modules deeply in processor core, we also refer to a testing methodology for the proposed processor to ensure our design functionality. The application of this processor is mainly focused on testing in SOC design.

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