中文摘要
系所別 : 電機工程學系 系統組
論文名稱: 一個具有線性相移器之六十五億赫茲鎖相迴路
指導教授: 朱大舜 博士
研究生 : 102061563 陳立偉

在軍用雷達之中，快速的偵測與反應為首要目的，傳統的機械式雷達因為在掃描上需要以旋轉的方式進行，可以達成的資訊更新速度有限，因此現在的主流雷達是使用可以電子式控制的相位陣列雷達，使用改變波形相位的方式，形成對目標物方向的建設性干涉雷達波，精準且有效的鎖定目標。
本文提出了一個可以使用CMOS晶片設計的鎖相迴路，以數位信號控制相位的機制，將這組數位信號以數位類比轉換器產生一個類比的控制訊號，控制壓控振盪器外加的可變電容，當這組可變電容改變容值時，迴路為了鎖回原來的頻率，會改變原來的壓控振盪器控制電壓，改變迴路控制的可變電容容值，在這裡利用這個控制電壓的改變來移動相位，使用的是互斥或閘來造成相位的移動。
因為所要設計的是屬於主動式相位陣列雷達，因此在CMOS晶片上同時會有鎖相迴路以及功率放大器，因此在迴路之中，為了避免了兩者的互相影響，避免在鎖相迴路之中產生功率放大器頻率的次諧波，所以採用了除1.5倍的除頻器，而設計這樣的除頻器無法達成50%的duty cycle，所以在互斥或閘之前先以相位頻率檢測器來比較頻率，完成改變相位的目的。
本文分為五個章節，第一章介紹本文的研究動機，第二章介紹與分析鎖相迴路的各部子電路原理，第三章敘述35GHz電流幫浦式鎖相迴路的實際設計與模擬結果及電路佈局，第四章討論加入線性相移器的鎖相迴路之電路設計與模擬結果；最後在第五章做出本文的結論，並歸納提出未來展望。

ABSTRACT
For the military radar, rapid detection and reaction are the primary purpose. traditional mechanical scanning radar needs to rotate the way, limited information update rate can be reached, so now the mainstream radar can use electronic control phased array radar, using the changed waveform phase manner, the formation of object orientation constructive interference radar, accurate and effective targeted.
This paper presents a CMOS chip design can use phase-locked loop for digital signal control mechanisms phase, this group of digital signals to digital-to-analog converter generates an analog control signals to control the voltage controlled oscillator plus a variable capacitor, When this set of variable capacitance change capacitance, the loop to lock back to the original frequency, will change the original VCO control voltage change leisurely loop control variable value, where the use of this change of control voltage to move phase, using exclusive-OR gate to cause the mobile phase.
Because of the design it is to belong to the active phased array radar, so there will be phase-locked loop and power amplifier on a CMOS wafer simultaneously, thus being in the loop, in order to avoid the mutual influence of the two, to avoid being in a phase-locked loop harmonic frequency power amplifier, so in addition to using a frequency divider-by-1.5, and the design of such frequency divider unable to reach a 50% duty cycle, so before the first exclusive or gate to the phase frequency detector to compare the frequency , the purpose of changing the phase is completed.

This paper is divided into five chapters, the first chapter introduces the research motivation of this article, the sub-circuit principle ministries and analysis of the second chapter of the phase-locked loop, the third chapter describes 35GHz current pump type phase-locked loop of the actual design and simulation results and circuit design and simulation circuit layout, the fourth chapter was added linear phase shift of the phase-locked loop; and finally make a conclusion in the fifth chapter, and summarizes proposed future prospects. 

[1] H. O. Johansson, "A Simple Prechar ge CMOS Phase Frequency Detector," IEEE Journ al of Solid Slate Circuits, vol. 33, no. 2, pp. 295-299, February.
1998.
[2] A. Homayoun and Behzad Razavi, "Analysis of Phase Noise in
Phase/F requency Detectors," IEEE Trans. on Circuits and Systems-I: regular papers, vol. 60, no. 3 pp. 529-539, March. 2013.
[3] N. Kalantari and M. M. Green, "All-CMOS high-speed CML gates withactive shunt-peaking, " in Proc. IEEE Int. Symp. Circuits Syst,pp. 2554–2557, May. 2007.
[4] P. Andreani, A. Bonfanti, L. Romanò, and C. Samori, "Analysis and design of a 1.8-GHz CMOS LC quadrature VCO, " IEEE J. Solid-State Circuits, vol. 37, pp. 1737–1747, Dec. 2002.
[5] Y. Mo, E. Skafidas, R. Evans, and I. Mareels, "Analysis and design ofa 50-GHz 2:1 CMOS CML static frequency divider based on LC-tank, " in Proc. Eur. Microw. Integr. Circuit Conf, pp. 64–67, Oct. 2008.
[5] S. Emami, C. H. Doan, A. M. Niknejad, and R. W. Brodersen, "A 60-GHz down-converting CMOS single-gate mixer, " 2005 IEEE M1T-S Int. Microwave Symp. Dig., pp. 163-166, June.2005.
[6] B. M. Motlagh, "Fully integrated 60-GHz single-ended resistivemixer in 90-nm CMOS technology," IEEE Microwave andWireless Components letter, vol. 16, no. 1, pp. 25-27, January.2006.
[7] M. S. Hwang, J. Kim, D.-K. Jeong. Reduction of pump current mismatch in charge-pump PLL. Electronics Letters, Vol.45, pp.135-136, Jan. 2009.

[8] A. Mirzaei, M. E. Heidari, and A. A. Abidi, "Analysis of oscillators locked by large injection signals: Generalized Adler’s quation and geometrical interpretation, " in Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp. 737–740, Sept.2006.
[9] F. Ellinger, R. Vogt, and W. Bächtold, "Compact, resistive monolithicintegrated mixer with low distortion for HIPERLAN, " IEEE Trans. Mi-crowave Theory Tech., vol. 50, pp. 178–182, Jan. 2002.
[10] R. Adler, "A study of locking phenomena in oscillators, " Proc. IEEE,vol. 61, pp. 1380–1385, Oct..1973.
[11] A. Homayoun and Behzad Razavi, "Analysis of Phase Noise in Phase/F requency Detectors," IEEE Trans. on Circuits and Systems-I: regular papers, vol. 60, no. 3, pp. 529-539, March 2013.
[12] W.-S. Chang , K.-W. Tan and S.-H. Hsu "A 56.5–72.2 Ghz transformer-injection Miller frequency divider in 1.3-um CMOS", IEEE Microw. WirelessCompon. Lett., vol. 20, no. 7, pp.393 -395,Jul. 2010.
[13] 高曜煌, 射頻鎖相迴路IC設計, 滄海書局, 2005
[14] 劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006
[15] Behzad Razavi, Design of analog CMOS integrated circuits, 2001