支援低功率測試與易診斷特性的掃瞄測試架構

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研究生：	曾昭文 Tzeng, Chao-Wen
論文名稱：	支援低功率測試與易診斷特性的掃瞄測試架構 Scan Architecture Supporting Low Power Test Compression and Easy Diagnosis
指導教授：	黃錫瑜 Huang, Shi-Yu
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	105
中文關鍵詞：	掃瞄測試、測試壓縮、低功率測試、無線測試、瑕疵診斷
外文關鍵詞：	Scan Test, Test Compression, Low Power Test, Wireless Test, Defect Diagnosis
相關次數：	點閱：1 下載：0
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掃瞄測試已經成為晶片測試中一種被廣泛應用的測試項目，但隨著晶片製造技術的提升，晶片本身的複雜度也日益提高，進而需要更大量的測試向量來進行測試以確保測試品質，而這卻意味著我們將需要更大量的掃瞄測試時間，及能乘載大量測試所需資料的測試機台，這都將大大的提高測試所需成本。因此，測試壓縮的技術 (Test Compression) 成為了掃瞄測試中不可或缺的設計。但是，在這些已開發的測試壓縮技術中，卻還有許多尚待解決的問題需要考慮，這其中包含了掃瞄測試過程中，會消耗過高功率的現象，此現象將影響晶片良率甚至對晶片早成永久性的傷害。此外，由於有線式傳統機台昂貴的價格及過高的測試成本等因素下，無線式的測試平台成了一個日益受到重視的測試方式，但是由於無線傳輸的速度限制，如何將需要大量資料傳輸的掃瞄測試方法應用到無線測試平台上成了無線測試的一個極需突破的瓶頸。而雖然壓縮技術可減少測試過程中對測試機台記憶體乘載量的需求，卻也造成我們無法取得完整的輸出端資料，此現象也將嚴重得影響瑕疵診斷的診斷結果。
因此這促使我們開發出一個更全面的掃瞄測試壓縮架構，此架構將能夠滿足快速且低功率的測試要求，並且在診斷時能夠提供更有效率且準確度更高的測試結果。首先我們開發了一套『萬用型群體廣播式掃瞄鍊測試架構』(Universal Multicasting Scan Test)，可以將測試時間的縮短倍數大幅提昇，並在此架構上，延伸出能兼具快速測試且低功率的測試技術 (Quick and Cool Scan Test)。此外，我們也提出如何將掃瞄測試方法應用到無線測試平台上。我們開發出更全面的壓縮技術來對測試資料進行壓縮，並同時兼顧測試與診斷的需求提出混合式輸出壓縮架構，使得掃瞄測試在無線測試平台上更有效率。而為了解決瑕疵診斷在測試壓縮環境下精確度過低的問題，我們提出一個掃瞄鍊分段隔離 (Split-Gating) 的架構，透過此架構，可解決在高壓縮倍率的需求下，瑕疵診斷精確度過低的問題。

Scan test has been an indispensable test methodology for guaranteeing test quality in industry. However, as the designs become larger and larger, the cost of scan test has been skyrocketing as the test data volume grows prohibitively high and thus increasing the test time proportionally. At the same time, excessive test power consumption is causing yield loss during the scan test. Moreover, diagnosis quality has degraded significantly when test compression is in use. In addition, it is often desirable to port the scan test methodology to a low cost indirect-access test environment.
Facing the above challenges, this thesis will focus on the development of comprehensive scan architecture so that it can meet the above stringent requirements, i.e., low-power test compression with good diagnostic capability while being portable to an indirect-access test environment. For test data volume reduction, we propose multicasting-based scan architecture named Universal Multicasting Scan (UMC-Scan). As compared to the most advanced multicasting-based architectures, the experimental results will demonstrate that the proposed architecture can significantly improve the test compression ratio. For reducing test power consumption, a post pattern generation flow named Quick-and-Cool X-fill (QC-Fill). The proposed X-fill method can properly utilize the don’t-care bits in the test patterns to simultaneously reduce the test power, while retaining high test compression ratio. For porting scan test to a wireless test platform, called HOY test platform, indirect-access scan architecture will be introduced to improve the test efficiency when scan test is adopted in an indirect-access test environment. Finally, for compensating the loss of diagnostic resolution resulting from output compaction, we propose an output masking scheme. The experimental results demonstrate the proposed scheme can recover the diagnostic resolution loss induced by an output compactor almost completely without sacrificing the compaction ratio.

Chapter 1     Introduction    1
1     Problem of Interest    1
2     Thesis Organization    3
Chapter 2     Background    5
1     Test Compression Architecture    5
2     Low Power Test Compression Scheme    8
3     Scan Test in Indirect-Access Test Platform    11
4     Defect Diagnosis with Output Compaction    13
Chapter 3     Test Compression Architecture    15
1     Introduction    15
2     Universal Multicasting Scan Methodology    16
2.1     Compatibility Analysis    19
2.2     Control Pattern Reduction    20
2.3     Partial Data Reuse    24
3     Detailed UMC-Controller    26
4     Experimental Results    28
4.1     Test Compression Ratio    28
4.2     Comparison Results    30
4.3     Application to Multiple Test Channels    32
5     Summary    33
Chapter 4     X-Fill for Low Power Test Compression    34
1     Introduction    34
2     Basic Architecture and Power Metrics    35
2.1     Multicasting Scan Architecture    35
2.2     Basic Power Metrics    35
3     Proposed QC-Fill Scheme    36
3.1     Low-Power Driven Clique Partitioning    37
3.2     Multicasting-Driven X-Filling    40
3.3     Clique Stripping for Low Capture Power    43
3.4     Clique Stripping for Low Shifting Power    45
4     Experimental Results    47
4.1     Random-Fill vs. QC-Fill    48
4.2     Adjacent-Fill vs. QC-Fill    49
4.3     Preferred-Fill vs. QC-Fill    49
4.4     UMC-Scan vs. QC-Fill    50
4.5     Overall Comparison Summary    50
4.6     Qualitative Comparison    51
5     Summary    54
Chapter 5     Indirect-Access Scan Test Architecture    55
1     Introduction    55
2     Overview of HOY Platform    56
3     Indirect-Access Scan (iScan) Architecture    57
3.1     Test Data Compression    57
3.2     Packet Overhead Reduction    61
3.3     Output Response Compaction    63
4     Experimental Results    64
5     Summary    67
Chapter 6     Diagnosis with Output Compaction    68
1     Introduction    68
2     Preliminary    69
2.1     Basic Diagnostic Flow for Compound Defect    69
2.2     Challenge of Defect Diagnosis    71
3     Proposed Output Masking Scheme    76
3.1     Observation and Motivation    76
3.2     Proposed Split-Masking Scheme    77
3.3     Analysis of Area Overhead    80
3.4     Analysis of Control Data Overhead    81
4     Operations of Split-Masking Architecture    82
4.1     Observable/Non-Observable Logic Fault Effects     82
4.2     Dynamic Configuration for Output Compactor    84
4.3     Diagnosis for Multiple Faulty Chains    86
5     Experimental Results    88
5.1     Compound Defect Diagnosis    89
5.2     Chain Diagnosis with Unknown Effect    93
6     Summary    95
Chapter 7     Conclusion    96
Bibliography    98

                                

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