近年來，在VLSI設計上，功率消耗已成為一項重要的課題。動態電源管理 (Dynamic Power Management)是一種常見的節省能源方法。然而，電源管理常伴隨著些許效能下降。因此，如何在功率消耗與效能之間取得平衡，便是一項重要的課題，我們的目標是希望能夠將效能缺失控制在10%以下，而盡可能去降低功率消耗。而以往的動態電源管理方法上，常重於以軟體設計方法，將問題映射至複雜的數學模型上以求得解答。然而，軟體方法對於處理器而言是一項極大的負擔。此篇論文提出了一個以硬體架構為基礎的動態電源管理模型，針對AES加密器設計一系列的管理方法。我們完整的建構出了一可調式的實驗環境，可根據不同的需求反覆實驗調整各項參數。除了基本的功率消耗考量以外，我們還將實做上可能碰到的各項實際情況如電源轉換效能及轉換功率也同時架構進去，以求得其結果合乎實際與精準。整體實驗環境是以SystemC建構，結果顯示我們的方法平均可減少53%的功率消耗，同時僅伴隨著6%的效能缺失，與我們設定的目標相符。日後此管理方法可將廣泛應用於通訊及安全的領域上。

Power dissipation has became a critical concern for present VLSI
design in recent years. DPM (Dynamic Power Management) is a common
methodology which can dynamically scale the power level of ASIC to
adapt their requirements at runtime. Unfortunately, power management
usually accompanies some performance degradation. So how to
eliminate the unnecessary power dissipation with minimum harm of
performance will become a significant challenge for designers. Many
preceding researches of DPM just focus on complicated mathematical
solutions, which are hard to implement in hardware. When DPM
methodologies are practiced in pure software, their efficiencies
highly rely on the operating system. Moreover, huge computation
overhead of DPM manipulation can become a burden of operation system
to diminish the ability of main processor. Hence, a hardware-based
DVFS power manager is proposed. Our structure contains simple
computations that can be easily implemented in hardware but still
maintain a well power managed facility. AES (Advanced Encryption
Standard) is our DPM object, which is a fast cryptological scheme.
Because this device does not always need the peak performance, it
provides chances to reduce its overall energy dissipation with an
appropriate DPM methodology. Different from traditional DPM
researches, our proposed methodology contains many practical
concerns like the level transition overhand or the power transform
efficiency. These crucial concerns make it closer to the reality,
but the complexity of DPM is also more difficult than others.
Addition to basic DPM research, we combine 3 novel strategies into
our primary DPM to handle some special situations. After these
exception handling, our final methodology can be more stronger than
the primitive one. In order to demonstrate our DPM efficiency, we
generate a serial of user-defined test patterns which contain a
variety of different workload distribution. For finding a general
best solution, we construct a SystemC model to experiment and
exploit many different DPM policies. The experimental results show
that our ideal energy reduction can achieve 59.3% by the offline
methodology, and the practical online methodology can reduce
53.0% energy dissipation with just 6.0% performance
degradation. With many practical concerns, our DPM methodology is
still much close to the ideal offline results.

[1] Luca Benini, Giovanni De Micheli and Enrico Macii, “Designing Low-Power Circuits:
Practical Recipes”, Circuits and Systems Magazine, IEEE, vol. 1, pp. 6-25, 2001.
[2] David Nguyen, Abhijit Davare, Michael Orshandky, David Chinnery, Brandon Thompson
and Kurt Keutzer, “Minimization of Dynamic and Static Power Through Joint
Assignment of Threshold Voltages and Sizing Optimization”, International Symposium
on Low Power Electronics and Design, pp. 158-163, Aug. 2003.
[3] Juan M. Cebri´an, Juan L. Arag´on and Jos´e M. Garc´ia, “Leakage Energy Reduction
in Value Predictors through Static Decay”, Parallel and Distributed Processing Symposium,
IEEE, pp. 1-7, 2007.
[4] Zhigang Hu, Philo Juang, Kevin Skadron and Douglas Clark Margaret Martonosi, “Applying
Decay Strategies to Branch Predictors for Leakage Energy Savings”, International
Conference on Computer Design, IEEE, pp. 442-445, 2002.
[5] Michel Goraczko, Jie Liu, Dimitrios Lymberopoulos, Slobodan Matic, Bodhi Priyantha
and Feng Zhao, “Energy-Optimal Software Partitioning in Heterogeneous Multiprocessor
Embedded Systems”, DAC, ACM/IEEE, pp 191-196, June, 2008.
[6] Changjiu Xian, Yung-Hsiang Lu and Zhiyuan Li, “Energy-Aware Scheduling for
Real-Time Multiprocessor Systems with Uncertain Task Execution Time”, DAC,
ACM/IEEE, pp 664-669, June, 2007.
[7] Ay¸se, Kıvılcım Co¸skun, Tajana ˇ Simuni´c Rosing, Keith A. Whisnant and Kenny C.
Gross, “Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs”,
Trans. on VLSI, IEEE, vol. 16, pp. 1127-1140, Sep. 2008.
[8] Yung-Hsiang Lu and Giovanni De Micheli, “Comparing System-Level Power Management
Policies”, Design and Test of Computers, IEEE, vol. 18, pp. 10-19, 2001.
[9] Luca Benini, Alessandro Bogliolo and Giovanni De Micheli, “A Survey of Design Techniques
for System-Level Dynamic Power Management”, Trans. on VLSI Systems, IEEE,
vol. 8, no. 3, pp. 299-316, June 2000.
[10] H.-A. Chuang, C.-T. Huang, “Design and Evaluation of a Power-Adaptive Methodology”,
Master Thesis, Dept. of Computer Science, National Tsing Hua University,
Hsinchu, Taiwan, Oct. 2008.
[11] Hwisung Jung and Massoud Pedram, “Continuous Frequency Adjustment Technique
Based on Dynamic Workload Prediction”, International Conference on VLSI Design,
IEEE, 2008.
[12] Peng Rong and Massoud Pedram, “Battery-Aware Power Management Based on Markovian
Decision Processes”, Trans. on CAD, IEEE, vol. 25, no. 7, pp. 1337-1349, July
2006.
[13] Hwisung Jung and Massoud Pedram, “Improving the Efficiency of Power Management
Techniques by Using Bayesian Classification”, International Symposium on Quality
Electronic Design, IEEE, 2008.
[14] Youngjin Cho and Naehyuck Chang, Chaitali Chakrabarti, Sarma Vrudhula, “High-
Level Power Management of Embedded Systems with Application-Specific Energy Cost
Functions”, DAC, IEEE, pp. 568-573, July 2006.
[15] T. D. Burd, T. A. Pering, A. J. Stratakos and R. W. Brodersen, “A Dynamice Voltage
Scaled Microprocessor System”, Journal of Solid-State Circuits, IEEE, vol. 35, no. 11,
pp. 1571-1580, Nov. 2000.
[16] Alexandru Andrei, Petru Eles, Zebo Peng, Marcus T. Schmitz and Bashir M. Al
Hashimi, “Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection”,
Trans. on VLSI, IEEE, vol. 15, no. 3, pp 262-275, March 2007.
[17] Zhen Cao, Brian Foo, Lei He and Mihaela van der schaar, “Optimality and Improvement
of Dynamic Voltage Scaling Algorithms for Multimedia Applications”, DAC, IEEE,
June, 2008.
[18] Reinaldo Bergamaschi, et al. “Exploring Power Management in Multi-Core Systems”,
Design Automation conference of Asia and South pacific(ASPDAC), pp. 708-713, Mar.
2008.
[19] Canturk Isci, Alper Buyuktosunoglu, Chen-Youn Cher, Pradip Bose and Margaret
Martonosi,“An Analysis of Efficient Multi-Core global Power Management Policies Maximizing
Performance for a Given Power Budget”, International Symposium on microarchitecture,
IEEE/ACM, pp.347-358, 2006.
[20] Ranjani Sridharan, Nikhil Gupta and Rabi Mahapatra, “Feedback-Controlled
Reliability-Aware Power Management for Real-Time Embedded Systems”, DAC, IEEE,
June, 2008.
[21] Ganesh Dasika, Shidhartha Das, Kevin Fan, Scott Mahlke and David Bull, “DVFS in
Loop Accelerators Using BLADES”, DAC, IEEE, June, 2008.
[22] R. Muresan, H. Vahedi, Y. Zhanrong and S. Gregori, “Power-Smart System-On-
Chip Architecture for Embedded Cryptosystems”, International Conference on Hardware/
Software codesign and system synthesis, IEEE/ACM/IFIP, pp. 184-189, 2005.
[23] Yan Gu, Samarjit Chakraborty and Wei Tsang Ooi, “Games are Up for DVFS”, DAC,
IEEE, July, 2006.
[24] Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steven G. Dropsho, Sandhya
Dwarkadas and Michael L. Scott, “Dynamic Frequency and Voltage Scaling for
a Multiple-Clock-Domain Microprocessor”, Micro. IEEE, pp. 62-68, 2003.
[25] Masakatsu Nakai, et al. “Dynamic Voltage and Frequency Management for a Low-Power
Embedded Microprocessor”, Journal of Solid-State Circuits, IEEE, vol. 40, no. 1, Jan.
2005.
[26] IEEE Educational Activities Department, “What is Cryptography?”, IEEE Security
and Privacy, vol. 4, issue 1, Jan, 2006.
[27] National Instutute of Strandards and Technology (NIST), Advanced Encryption Standard
(AES), National Technical Information Service, Springfield, VA 22161, Nov. 2001.
[28] Jyu-Yuan Lai and Chih-Tsun Huang, “Elixir: High-Throughput Cost-Effective Dual-
Field Processors and the Design Framework for Elliptic Curve Cryptography”, Trans.
on VLSI, IEEE, pp. 1567-1580, June, 2008.
[29] Z.-H. Shen, C.-T. Huang, “Design of a Power-Aware AES Cipher”, Master Thesis, Dept.
of Computer Science, National Tsing Hua University, Hsinchu, Taiwan, July. 2007.
[30] C.-P. Su, T.-F. Lin, C.-T. Huang and C.-W. Wu, “A highly efficient AES cipher chip”,
Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), pp. 561-562, Kitakyushu,
Jan. 2003.
[31] S.-Y. Lin and C.-T. Huang, “A High-Throughput Low-Power AES Cipher for Network
Applications”, Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), pp.
595-600, 2007.
[32] Bor-Tyng Lin, Ruei-Wun Sun and Hsi-Pin Ma, “A low power/low voltage standard cell
library design for digital integrated circuit”, VLSI Design/CAD Symposium, Aug. 2008.
[33] S. Zhou, G. A. Rinc´on-Mora, “A High Efficiency, Soft Switching DC-DC Converter
With Adaptive Current-Ripple Control for Portable Applications”, Trans. on Circuits
and Systems, IEEE, Vol. 53, No. 4, pp. 319-323, 2006.
[34] Puru Choudhary, Diana Marculescu, “Power Management of Voltage/Frequency Island-
Based Systems Using Hardware-Based Methods”, Trnas. on VLSI, IEEE, vol. 17, no.
3, pp. 427-438, March 2009.
[35] Amit Sinha and Anantha P. Chandrakasan, “Dynamic Voltage Scheduling Adaptive
Filtering of Worklaod Traces”, Conf. in VLSI Design, IEEE, pp. 221-226, Jan. 2001.
[36] Yan Gu and Smamrjit chakraborty, “Control Theory-based DVS for Interactive 3D
Games”, DAC, IEEE, June, 2008.
[37] Design Automation Standards Committee of the IEEE Computer Society, IEEE Std
1666 - 2005 IEEE Standard SystemC Language Reference Manual, 2006.
[38] M. Najibi, M. Salehi, A. A. Kusha, M. Pedram, S. M. Fakhraie and H. Pefram, “Dynamic
Voltage and Frequency Management Based on Variable Update Intervals for
Frequency Setting”, Proc. of IEEE/ACM international conference on Computer-aided
design (ICCAD), pp. 755-760, 2006.