此論文著重在積體電路的傳導式電磁相容的寬頻量測技術開發，並提出了晶片層級的設計對策，首先針對電磁干擾測試，提出符合IEC61967-4標準的1-Ω探棒，其介入損耗可在1 GHz的頻寬內滿足34±2 dB的規格需求，為了滿足高速高頻的測試需求，突破性地提出裸晶量測的架設，以積體被動元件製程實現的1-Ω電流探棒與150-Ω電壓探棒頻寬可達15 GHz，再利用覆晶技術將待測IC進行晶片層級的電磁干擾測試。為克服傳統被動式1-Ω探棒的高損耗，提出一主動式的1-Ω探棒，透過精準的1-Ω電阻設計與寬頻放大器的整合，使損耗由傳統的34 dB降低至18 dB，其應用頻寬可達3 GHz，利用一微處理器晶片作為待測物，量測結果顯示主動探棒可較傳統被動探棒具備更佳的雜訊偵測能力。在電磁耐受度方面，針對IEC 62132-4標準的直接功率注入法，將量測頻寬自1 GHz延展到18 GHz，透過對一線性穩壓IC進行測試，證明超過IC操作頻率之高頻訊號仍會導致電路的誤動作。最後，此論文提出了兩個應用於晶片層級的電磁相容解決方案，轉動率控制電路改變信號邊緣上升與下降速率，降低訊號在頻譜的高頻分量而改善電磁干擾的問題，另外，提出MOS與MOM堆疊的去耦合電容，其電容量相較於MOS電容可獲得17%的提升，將其嵌入於線性穩壓器晶片中，其耐受能力最大可達11.6 dB的改善。

This work focuses on the wideband measurement technique development of the conducted electromagnetic compatibility (EMC) for IC, and presents the chip level design strategies. For the electromagnetic interference (EMI) test, a 1-Ω probe is presented to comply with the IEC61967-4 standard. The insertion loss specification of 34±2 dB is achieved within 1 GHz bandwidth. To meet the demand of high speed/high frequency testing, the on-chip test setup is proposed. By implementing the 1-Ω current probe and 150-Ω voltage probe in the integrated passive device (IPD) technology, the bandwidth could reach up to 15 GHz. With the flip-chip technology, the chip level EMI test is performed. Furthermore, an active 1-Ω probe is proposed to overcome the high loss property of the conventional passive probe. By integrating the precise 1-Ω resistor design and a wide band amplifier, the insertion loss is reduced form 34 dB to 18 dB with the operating bandwidth of 3 GHz. A MCU chip is tested to demonstrate that the active probe shows a better ability of detecting interference than the conventional passive probe. For the electromagnetic susceptibility (EMS) test, the bandwidth of the IEC62132-4 standard, the direct power injection (DPI) method, is extended from 1 GHz to 18 GHz. A linear low dropout regulator (LDO) IC is tested to demonstrate that the IC would still malfunction when it encounters with the interference at the frequency higher than its operating frequency. Finally, two chip level EMC solutions are proposed. The slew rate controller could change the rising/falling rate of a signal. It reduces the high frequency contents of the signal and results in the improved EMI issue. Besides, a decoupling capacitor (decap) which stacks MOM and MOS capacitors is proposed. It provides extra 17% capacitance compared with the MOS capacitor. By embedding the proposed decaps into a LDO, the immunity can be improved with a maximum value of 11.6 dB.

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