電源閘設計是一個讓漏電流減少很有效的方法。之前有一個稱做分散式睡眠電晶體網路(DSTN)的方法被提出，他的作法是把所有的虛擬接地線連起來，減少通過睡眠電晶體的瞬時最大電流。在這篇論文當中，我們提出一個新的方法去決定分散式睡眠電晶體網路中睡眠電晶體的大小。我們提出一些新的演算法和定理去精確估計電壓降的上限。我們也提出了一些技巧去減少睡眠電晶體的大小。我們的實驗結果證實我們的方法確實能夠符合電壓降的限制。

Power gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current (MIC) through sleep transistors. In this thesis, we propose a new methodology for determining the size of sleep transistors for the DSTN structure. We present novel algorithms and theorems for efficiently estimating a tight upper bound of the voltage drop. We also present efficient heuristics for minimizing the sizes of sleep transistors. Our experimental results are very exciting.

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