鎖相迴路已經是目前不可或缺的重要時脈產生器來源，尤其是在無線通訊收發器中，鎖相迴路被用來當作頻率合成器，合成出不同的頻率時脈與所接受到的高頻信號相乘，進而降頻至基頻進行信號處理，為了因應頻道間距以及通訊品質，頻率合成器的頻率解析度和相位雜訊是時脈設計很重要的考量因素。
　　由於典型的整數型鎖相迴路頻率解析度受限於參考時脈，因此頻率合成器必須使用三角積分鎖相迴路來完成，但其平均的概念伴隨著量化雜訊，許多技術發展出來抑制這些雜訊，其中提高三角積分器的超採樣率，將量化雜訊移至更高頻率被濾波的方法是本論文主要採用的技術。
　　有別於已發表的高超採樣率三角積分鎖相迴路，本論文首先分析除頻器與頻率偵測器之間的離散與連續時間轉換介面，並且為此介面的行為設計了因應的數位有限脈衝響應濾波器在三角積分器的輸出，並且搭配所提出的半整數除頻器，以抑制量化雜訊，並且在特定頻率有更進一步的濾波效果，相較於傳統的三階三角積分鎖相迴路的量化雜訊有21 dB的抑制量。
　　晶片是使用台積電 180 nm CMOS 混合信號製程所設計，頻率合成器頻率範圍為 2.58 GHz 到 3.45 GHz ，核心電路功率消耗約為 12 mW ，量測時搭配 FPGA 板來實現三角積分調變器以及有限脈衝響應濾波器，量測結果驗證了在 1/5 及 3/5 倍參考頻率處有更進一步的濾波效果。

In modern wireless communication systems, frequency synthesizers with high frequency resolution are used to up/downconvert signals to desired bands precisely. Phase-locked loops (PLLs) with the delta-sigma technique are a common way to achieve high frequency resolution. However, quantization noise is inevitable introduced during division ratio dithering, it greatly degrades the out-band noise performance especially in a high-bandwidth phase-locked loop.
We focus on the study of quantization noise suppression. Analysis of quantization noise from delta-sigma modulation and the interface between continuous-time and discrete-time signal processing in PLLs plays an important role in this thesis. Based on this analysis, we propose a high oversampling rate (H-OSR) delta-sigma frequency synthesizer on which an finite-impulse response (FIR) digital filter and a novel half-integer frequency based on the phase compensation technique are embedded.
The simulation result shows that the proposed architecture is able to suppress the quantization noise by 21 dB compared with the conventional MASH 1-1-1 structure. Moreover, the notch filtering effect from the FIR filter can further reduce quantization noise at the specific frequency, and improve the phase jitter performance.
The proposed frequency synthesizer was verified by the silicon results in a TSMC 0.18μm CMOS process. Output frequency range is from 2.58 GHz to 3.45 GHz, the core power consumption is 12 mW. At the frequency of 1/5 and 3/5 reference frequency in the phase noise spectrum, the notch filtering effect can be found. Besides, FPGA is used to implement the delta-sigma modulator and the FIR filter during the measurement.

參考文獻
[1] B. Razavi, RF Microelectronics, Pretice-Hall, Inc., 1998.
[2] Y.-H. Kao, RF Phase-Locked Loop Integrated Circuit Design, Tsang-Hai Book Publishing Co., 2004.
[3] Lacaita, A. Leonardo, S. Levantino, and C. Samori, Integrated Frequency Synthesizers for Wireless Systems, Cambridge University Press, 2007.
[4] B. Razavi, Design of Analog CMOS Integrated Circuits. Mc Graw Hill, 2001.
[5] A. V. Oppenheim, R. W. Schafer, and J. R. Buck, Discrete-time signal processing (2nd ed.), Prentice-Hall, Inc., 1999.
[6] W. Rhee, B.-S. Song, and A. Ali, "A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order delta sigma modulator," Solid-State Circuits, IEEE Journal of, vol.35, no.10, pp.1453-1460, Oct. 2000.
[7] B. Miller and R. J. Conley, "A multiple modulator fractional divider," Instrumentation and Measurement, IEEE Transactions on, vol.40, no.3, pp.578-583, Jun 1991.
[8] S. E. Meninger and M. H. Perrott, "A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise," Solid-State Circuits, IEEE Journal of , vol.41, no.4, pp.966-980, April 2006.
[9] S. Pamarti, L. Jansson, and I. Galton, "A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation," Solid-State Circuits, IEEE Journal of, vol.39, no.1, pp.49-62, Jan. 2004.
[10] Y.-C. Yang, S.-A. Yu, Y.-H. Liu, T. Wang, and S.-S. Lu, "A Quantization Noise Suppression Technique for ΔΣ Fractional- N Frequency Synthesizers," Solid-State Circuits, IEEE Journal of, vol.41, no.11, pp.2500-2511, Nov. 2006.
[11] L. Lu, Z. Gong, Y. Liao, H. Min, and Z. Tang, "A 975-to-1960MHz fast-locking fractional-N synthesizer with adaptive bandwidth control and 4/4.5 prescaler for digital TV tuners," Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, vol., no., pp.396-397,397a, 8-12 Feb. 2009.
[12] B. A. Floyd, "A 16–18.8-GHz Sub-Integer-N Frequency Synthesizer for 60-GHz Transceivers," Solid-State Circuits, IEEE Journal of, vol.43, no.5, pp.1076-1086, May 2008.
[13] J. Jin, X. Liu, T. Mo, and J. Zhou, "Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol.59, no.5, pp.926-937, May 2012.
[14] J. Shin, I. Seo, J. Kim, S.-H. Yang, C. Kim, J. Pak, H. Kim, M. Kwak, and G. Hong, "A Low-Jitter Added SSCG with Seamless Phase Selection and Fast AFC for 3rd Generation Serial-ATA," Custom Integrated Circuits Conference, 2006. CICC '06. IEEE, vol., no., pp.409-412, 10-13 Sept. 2006.
[15] P. Park, D. Park, and S. Cho, "A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL," Solid-State Circuits, IEEE Journal of, vol.47, no.10, pp.2433-2443, Oct. 2012.
[16] Y.-C. Yang and S.-S. Lu, "A Quantization Noise Pushing Technique for ΔΣ Fractional-N Frequency Synthesizers," Microwave Theory and Techniques, IEEE Transactions on, vol.56, no.4, pp.817-825, April 2008.
[17] D. Banerjee, PLL Performance, Simulation, and Design, Santa Clara, CA: Nat. Semiconduct., 2006.
[18] A. D. Berny, A. M. Niknejad, and R. G. Meyer, "A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration," Solid-State Circuits, IEEE Journal of, vol.40, no.4, pp.909-917, April 2005.
[19] T.-H. Lin and Y.-J. Lai, "An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL," Solid-State Circuits, IEEE Journal of, vol.42, no.2, pp.340-349, Feb. 2007.
[20] T. A. D. Riley, N. M. Filiol, Q. Du, and J. Kostamovaara, "Techniques for in-band phase noise reduction in ΔΣ synthesizers," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , vol.50, no.11, pp.794-803, Nov. 2003.
[21] B. De Muer and M. S. J. Steyaert, "A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800," Solid-State Circuits, IEEE Journal of, vol.37, no.7, pp.835-844, Jul 2002.
[22] C.-H. Heng and B.-S. Song, "A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO," Solid-State Circuits, IEEE Journal of, vol.38, no.6, pp.848-854, June 2003.
[23] S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, "A family of low-power truly modular programmable dividers in standard 0.35-µm CMOS technology," Solid-State Circuits, IEEE Journal of , vol. 35, no. 7, pp. 1039-1045, Jul. 2000.
[24] W. Rhee and A. Ali, "An on-chip phase compensation technique in fractional-N frequency synthesis," Circuits and Systems, ISCAS '99. Proceedings of the 1999 IEEE International Symposium on, vol.3, no., pp.363-366 vol.3, Jul 1999.
[25] S. Levantino, L. Romano, S. Pellerano, C. Samori, and A. L. Lacaita, "Phase noise in digital frequency dividers," Solid-State Circuits, IEEE Journal of , vol.39, no.5, pp.775-784, May 2004.
[26] T.-H. Chien, C.-S. Lin, C.-L. Wey, Y.-Z. Juang, and C.-M. Huang, "High-speed and low-power programmable frequency divider," Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, vol., no., pp.4301-4304, May 30 2010-June 2 2010.
[27] S. Kim, K. Lee, Y. Moon, D.-K. Jeong, Y. Choi, and H.-K. Lim, "A 960 Mbps/pin interface for skew-tolerant bus using low jitter PLL," VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on, vol., no., pp.118-119, 13-15 June 1996.
[28] W. Rhee, "Design of high-performance CMOS charge pumps in phase-locked loops," Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on, vol.2, no., pp.545-548 vol.2, Jul 1999.
[29] C. Quemada, G. Bistue, and I. Adin, Design Methodology for RF CMOS Phase Locked Loops, Artech House, Inc., 2009.