製造貨批量變動之製造系統模擬與資料挖礦以一面板廠為實證研究

簡易檢索 / 詳目顯示

回結果列表

研究生：	王人星
論文名稱：	製造貨批量變動之製造系統模擬與資料挖礦以一面板廠為實證研究 Manufacturing Data Mining for Lot Size Variation by A Simulation Model: An Empirical Study on TFT-LCD Manufacturing
指導教授：	簡禎富
口試委員:
學位類別：	碩士 Master
系所名稱：	工學院 - 工業工程與工程管理學系 Department of Industrial Engineering and Engineering Management
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	44
中文關鍵詞：	半導體製程、TFT-LCD製程、資料挖礦、在製品等級
外文關鍵詞：	semiconductor manufacturing, TFT-LCD manufacturing, data mining, WIP level
相關次數：	點閱：2 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

摘要
隨著高科技產業，包括半導體產業以及TFT-LCD產業，進入微利的時代，許多研究開始實驗製造批量大小的改變來降低週期時間與成本。高科技產業中，半導體製程與TFT-LCD製程有些相似的特性，本研究的目的以一模擬真實的TFT-LCD廠模型為基礎於實驗TFT-LCD廠中的製造批量大小來觀察其變化對於績效指標的影響，本研究並運用資料挖礦的方法來找出在製程中的關鍵機台，並且整理有效的資訊蒐集有效的模式。因此藉由分析的結果，本研究也擬出一較好的在製品等級配置及討論相關的應用。

關鍵字：半導體製程、TFT-LCD製程、資料挖礦、在製品等級

Abstract
As high-tech industry including semiconductor manufacturing industry breaks into a tiny-profit age, many studies examine lot size variation to decrease cycle time and cost. High-tech industry including semiconductor and TFT-LCD manufacturing industry has similar manufacturing properties, this study aims to examine and monitor the lot size variation to study its impacts on performance indexes. Based on a fab simulation model, in this research also use data mining approach to find out critical machines in the manufacturing process and extract potential useful patterns. Thus, we will try to suggest better WIP level arrangement on the basis of the results. We have employed this approach in a real TFT-LCD fab as an empirical study for validation.

Key words: Semiconductor manufacturing, TFT-LCD manufacturing, Data mining approach, WIP level

Table of Contents
Chapter 1 Introduction    1
1.1 Background, significance and motivation    1
1.2 Research aims    2
1.3 Overview of this thesis    3
Chapter 2 Literature Review    4
2.1 Some critical factors in semiconductor manufacturing    4
2.2 Data mining    8
2.2.1 Self-organize feature map (SOM)    10
2.2.2 Clustering analysis    12
2.3 The SWP properties in the semiconductor manufacturing    15
2.4 Simulation    16
Chapter 3 Conceptual Framework    18
3.1 Problem Understanding    20
3.1.1 Problem definition and structuring    20
3.1.2 System understanding    22
3.1.3 Data preparation    23
3.2 Model Construction    25
3.2.1 Indices    25
3.2.3 Simulation Model Building    28
3.3 Experiment and Analysis    29
3.3.1 Simulation experiment    29
3.3.2 Data mining approach: SOM    29
Chapter 4 An Illustrative Study    30
4.1 Simulation Model Details    30
4.2 Result analysis with data mining approach    34
4.2.1 Performance index    34
4.2.2 Bottleneck analysis    35
4.2.3 WIP level decision    40
Chapter 5 Conclusion    42
References    43


Figure List
Figure 2.1 the repeated steps of data mining (Berry et al., 1997)    9
Figure 3.1 Conceptual Framework    19
Figure 3.2 Mini-Fab typical reentrant flow structure    22
Fig. 4.1 The simulation model    34
Fig. 4.2 Machine utilization cluster by SOM (20 pcs)    36
Fig. 4.3 Machine utilization cluster by SOM (10 pcs)    37
Fig. 4.4 Machine utilization cluster by SOM (5 pcs)    38
Fig. 4.5 CT to WIP graph    40
Fig. 4.6 TH to WIP graph    41
Table List
Table 2.1 The definitions of variety distance measures    13
Table 3.1 Data preparation requirement    25
Table 4.1 Machine ID and quantities    30
Table 4.2 Standard operation time (mins) of each machine by lot (20pcs/lot)    31
Table 4.3 Performance indexes in each scenario    35
Table 4.4 Rank by utilization (20pcs)    35
Table 4.5 Rank by utilization (10pcs)    37
Table 4.6 Rank by utilization (5pcs)    38

                                

References
Wein, L. M. (1988), “Scheduling semiconductor wafer fabrication”, IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No.3.
Perkinson, T. L., McLarty, P. K., Gyurcsik, R. S., and Cavin, R. K. (1994), “Single-wafer cluster tool performance: an analysis of throughput”, IEEE Transactions on Semiconductor Maunfacturing, Vol. 7, No. 3.
Lu, S. C. H., Ramaswamy, D., and Kumar, P. R. (1994), “Efficient scheduling policies to reduce mean and variance of cycle time in semiconductor manufacturing plants”, IEEE Transactions on Semiconductor Manufacturing, Vol. 7, No. 3.
Perkinson, T. L., McLarty, P. K., Gyurcsik, R. S. (1996), “Single-wafer cluster tool performance: an analysis of the effects of redundant chambers and revisitation sequences on throughput”, IEEE Transactions on Semiconductor Manufacturing, Vol. 9, No. 3.
Leachman, R. C. (1997), “Closed-loop measurement of equipment efficiency and equipment capacity”, IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No. 1.
Wood, S. C. (1997), “Cost and cycle time performance of fabs based on integrated single-wafer processing”, IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No. 1.
Dabbas, R. M., and Chen, H. N. (2001), “Mining semiconductor manufacturing data for productivity improvement--- an integrated relational database approach”, Computers in Industry, pp. 29-44
Kwak, C. and Yih, Y. (2001), “Simulation comparison of collaboration protocol-based testing models”, International Journal of Production Research, Vol. 39, No. 13, pp. 2947-2956
Dabbas, R. M. and Fowler, J. W. (2003), “A new scheduling approach using combined dispatching criteria in wafer fabs”, IEEE Transactions on Semiconductor Manufacturing, Vol. 16, No. 3.
Ikeda, S., Nemoto, K., Funabashi, M., Uchino, T., Yamamoto, H., Yabuoshi, N., Sasaki, Y., Komori, K., Suzuki, N., Nishihara, S., Sasabe, S., and Koike, A. (2003), “Process integration of single-wafer technology in a 300-mm fab, realizing drastic cycle time reduction with high yield and excellent reliability”, IEEE Transactions on Semiconductor Manufacturing, Vol. 16, No. 2.
Jacobs, J. H., Etman, L. F. P., Campen, E. J. J., and Rooda, J. E. (2003), “Characterization of operation time variability using effective processing times”, IEEE Transactions on Semiconductor Manufacturing, Vol. 16, No. 3.
Min, H. S., and Yih, Y. (2003), “Development of a real-time multi-objective scheduler for a semiconductor fabrication system”, International Journal of Production Research, Vol. 41, No. 10, pp. 2345-2364.
Bonnin, O., Mercier, D., Levy, D., Henry, M., Pouilloux, I., and Mastromatteo, E. (2003), “Single-wafer/ mini-batch approach for fast cycle time in advanced 300-mm fab”, IEEE Transactions on Semiconductor Manufacturing, Vol. 16, No. 2.
Wein, L. M. (1992), “On the relationship between yield and cycle time in semiconductor wafer fabrication”, IEEE Transactions on Semiconductor Manufacturing, Vol. 5, No. 2.
Koonce, D. A., and Tsai, S. C. (2000), “Using data mining to find patterns in genetic algorithm solutions to a job shop schedule”, Computers and Industrial Engineering, pp. 361-374

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文